[PATCH] D29639: [SelectionDAG] Add a signed integer absolute ISD node

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.
Herald added subscribers: igorb, aemerson.

Reduced version of https://reviews.llvm.org/D26357 - based on the discussion on llvm-dev about canonicalization of UMIN/UMAX/SMIN/SMAX as well as ABS I've reduced that patch to just the ABS ISD node (with x86/sse support) to improve basic combines and lowering.

AFAICT ARM/AArch64, PowerPC and NVPTX all have similar instructions so I'd like to make this a generic opcode and move us away from the hard coded tablegen patterns which makes it tricky to match more complex patterns.

At the moment this patch doesn't attempt legalization (and I only create an ABS node if its legal/custom) - I can add the legalization code from https://reviews.llvm.org/D26357 if people think it useful at this stage - it will let us do some extra combines, knownbits handling etc.


Repository:
  rL LLVM

https://reviews.llvm.org/D29639

Files:
  include/llvm/CodeGen/ISDOpcodes.h
  include/llvm/Target/TargetSelectionDAG.td
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
  lib/CodeGen/TargetLoweringBase.cpp
  lib/Target/X86/X86ISelLowering.cpp
  lib/Target/X86/X86ISelLowering.h
  lib/Target/X86/X86InstrAVX512.td
  lib/Target/X86/X86InstrFragmentsSIMD.td
  lib/Target/X86/X86InstrSSE.td
  lib/Target/X86/X86IntrinsicsInfo.h
  test/CodeGen/X86/combine-abs.ll
  test/CodeGen/X86/viabs.ll

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