[llvm] r294226 - [Hexagon] Update MCTargetDesc
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 6 15:23:20 PST 2017
Hopefully r294296 will take care of this.
-Krzysztof
On 2/6/2017 4:41 PM, Vitaly Buka wrote:
> This patch introduced memory leaks and "left shift of negative value -1"
> http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/2579
>
> On Mon, Feb 6, 2017 at 11:47 AM Krzysztof Parzyszek via llvm-commits
> <llvm-commits at lists.llvm.org <mailto:llvm-commits at lists.llvm.org>> wrote:
>
> Author: kparzysz
> Date: Mon Feb 6 13:35:46 2017
> New Revision: 294226
>
> URL: http://llvm.org/viewvc/llvm-project?rev=294226&view=rev
> Log:
> [Hexagon] Update MCTargetDesc
>
> Changes include:
> - Updates to the instruction descriptor flags.
> - Improvements to the packet shuffler and checker.
> - Updates to the handling of certain relocations.
> - Better handling of duplex instructions.
>
> Added:
> llvm/trunk/test/MC/Hexagon/common-redeclare.s
> llvm/trunk/test/MC/Hexagon/dcfetch-symbol.s
> llvm/trunk/test/MC/Hexagon/equ.s
> llvm/trunk/test/MC/Hexagon/extended_relocations.ll
> llvm/trunk/test/MC/Hexagon/missing_label.s
> llvm/trunk/test/MC/Hexagon/non-relocatable.s
> llvm/trunk/test/MC/Hexagon/not-over.s
> llvm/trunk/test/MC/Hexagon/not_found.s
> llvm/trunk/test/MC/Hexagon/offset.s
> llvm/trunk/test/MC/Hexagon/operand-range.s
> llvm/trunk/test/MC/Hexagon/reg_altnames.s
> Modified:
> llvm/trunk/lib/Target/Hexagon/Hexagon.td
> llvm/trunk/lib/Target/Hexagon/HexagonInstrFormats.td
> llvm/trunk/lib/Target/Hexagon/HexagonInstrFormatsV4.td
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCCompound.cpp
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.h
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCExpr.cpp
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.cpp
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.h
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.h
> llvm/trunk/test/MC/Hexagon/dis-duplex-p0.s
> llvm/trunk/test/MC/Hexagon/relocations.s
>
> Modified: llvm/trunk/lib/Target/Hexagon/Hexagon.td
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/Hexagon.td?rev=294226&r1=294225&r2=294226&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/Hexagon.td (original)
> +++ llvm/trunk/lib/Target/Hexagon/Hexagon.td Mon Feb 6 13:35:46 2017
> @@ -27,9 +27,9 @@ def ArchV5: SubtargetFeature<"v5", "He
> def ArchV55: SubtargetFeature<"v55", "HexagonArchVersion", "V55",
> "Hexagon V55">;
> def ArchV60: SubtargetFeature<"v60", "HexagonArchVersion", "V60",
> "Hexagon V60">;
>
> -def FeatureHVX: SubtargetFeature<"hvx", "UseHVXOps", "true",
> +def ExtensionHVX: SubtargetFeature<"hvx", "UseHVXOps", "true",
> "Hexagon HVX instructions">;
> -def FeatureHVXDbl: SubtargetFeature<"hvx-double", "UseHVXDblOps",
> "true",
> +def ExtensionHVXDbl: SubtargetFeature<"hvx-double", "UseHVXDblOps",
> "true",
> "Hexagon HVX Double instructions">;
> def FeatureLongCalls: SubtargetFeature<"long-calls",
> "UseLongCalls", "true",
> "Use constant-extended calls">;
> @@ -46,10 +46,10 @@ def HasV60T : Predicate<"HST-
> def UseMEMOP : Predicate<"HST->useMemOps()">;
> def IEEERndNearV5T : Predicate<"HST->modeIEEERndNear()">;
> def UseHVXDbl : Predicate<"HST->useHVXDblOps()">,
> - AssemblerPredicate<"FeatureHVXDbl">;
> + AssemblerPredicate<"ExtensionHVXDbl">;
> def UseHVXSgl : Predicate<"HST->useHVXSglOps()">;
> def UseHVX : Predicate<"HST->useHVXSglOps()
> ||HST->useHVXDblOps()">,
> - AssemblerPredicate<"FeatureHVX">;
> + AssemblerPredicate<"ExtensionHVX">;
>
> //===----------------------------------------------------------------------===//
> // Classes used for relation maps.
> @@ -271,7 +271,7 @@ def : Proc<"hexagonv5", HexagonModelV4,
> def : Proc<"hexagonv55", HexagonModelV55,
> [ArchV4, ArchV5, ArchV55]>;
> def : Proc<"hexagonv60", HexagonModelV60,
> - [ArchV4, ArchV5, ArchV55, ArchV60, FeatureHVX]>;
> + [ArchV4, ArchV5, ArchV55, ArchV60, ExtensionHVX]>;
>
> //===----------------------------------------------------------------------===//
> // Declare the target which we are implementing
>
> Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrFormats.td
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrFormats.td?rev=294226&r1=294225&r2=294226&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/HexagonInstrFormats.td (original)
> +++ llvm/trunk/lib/Target/Hexagon/HexagonInstrFormats.td Mon Feb 6
> 13:35:46 2017
> @@ -13,8 +13,8 @@
> // *** Must match HexagonBaseInfo.h ***
> //===----------------------------------------------------------------------===//
>
> -class IType<bits<5> t> {
> - bits<5> Value = t;
> +class IType<bits<6> t> {
> + bits<6> Value = t;
> }
> def TypePSEUDO : IType<0>;
> def TypeALU32 : IType<1>;
> @@ -99,85 +99,85 @@ class InstHexagon<dag outs, dag ins, str
>
> // Instruction type according to the ISA.
> IType Type = type;
> - let TSFlags{4-0} = Type.Value;
> + let TSFlags{5-0} = Type.Value;
>
> // Solo instructions, i.e., those that cannot be in a packet with
> others.
> bits<1> isSolo = 0;
> - let TSFlags{5} = isSolo;
> + let TSFlags{6} = isSolo;
> // Packed only with A or X-type instructions.
> bits<1> isSoloAX = 0;
> - let TSFlags{6} = isSoloAX;
> + let TSFlags{7} = isSoloAX;
> // Only A-type instruction in first slot or nothing.
> bits<1> isSoloAin1 = 0;
> - let TSFlags{7} = isSoloAin1;
> + let TSFlags{8} = isSoloAin1;
>
> // Predicated instructions.
> bits<1> isPredicated = 0;
> - let TSFlags{8} = isPredicated;
> + let TSFlags{9} = isPredicated;
> bits<1> isPredicatedFalse = 0;
> - let TSFlags{9} = isPredicatedFalse;
> + let TSFlags{10} = isPredicatedFalse;
> bits<1> isPredicatedNew = 0;
> - let TSFlags{10} = isPredicatedNew;
> + let TSFlags{11} = isPredicatedNew;
> bits<1> isPredicateLate = 0;
> - let TSFlags{11} = isPredicateLate; // Late predicate producer insn.
> + let TSFlags{12} = isPredicateLate; // Late predicate producer insn.
>
> // New-value insn helper fields.
> bits<1> isNewValue = 0;
> - let TSFlags{12} = isNewValue; // New-value consumer insn.
> + let TSFlags{13} = isNewValue; // New-value consumer insn.
> bits<1> hasNewValue = 0;
> - let TSFlags{13} = hasNewValue; // New-value producer insn.
> + let TSFlags{14} = hasNewValue; // New-value producer insn.
> bits<3> opNewValue = 0;
> - let TSFlags{16-14} = opNewValue; // New-value produced operand.
> + let TSFlags{17-15} = opNewValue; // New-value produced operand.
> bits<1> isNVStorable = 0;
> - let TSFlags{17} = isNVStorable; // Store that can become
> new-value store.
> + let TSFlags{18} = isNVStorable; // Store that can become
> new-value store.
> bits<1> isNVStore = 0;
> - let TSFlags{18} = isNVStore; // New-value store insn.
> + let TSFlags{19} = isNVStore; // New-value store insn.
> bits<1> isCVLoadable = 0;
> - let TSFlags{19} = isCVLoadable; // Load that can become cur-value
> load.
> + let TSFlags{20} = isCVLoadable; // Load that can become cur-value
> load.
> bits<1> isCVLoad = 0;
> - let TSFlags{20} = isCVLoad; // Cur-value load insn.
> + let TSFlags{21} = isCVLoad; // Cur-value load insn.
>
> // Immediate extender helper fields.
> bits<1> isExtendable = 0;
> - let TSFlags{21} = isExtendable; // Insn may be extended.
> + let TSFlags{22} = isExtendable; // Insn may be extended.
> bits<1> isExtended = 0;
> - let TSFlags{22} = isExtended; // Insn must be extended.
> + let TSFlags{23} = isExtended; // Insn must be extended.
> bits<3> opExtendable = 0;
> - let TSFlags{25-23} = opExtendable; // Which operand may be extended.
> + let TSFlags{26-24} = opExtendable; // Which operand may be extended.
> bits<1> isExtentSigned = 0;
> - let TSFlags{26} = isExtentSigned; // Signed or unsigned range.
> + let TSFlags{27} = isExtentSigned; // Signed or unsigned range.
> bits<5> opExtentBits = 0;
> - let TSFlags{31-27} = opExtentBits; //Number of bits of range
> before extending.
> + let TSFlags{32-28} = opExtentBits; //Number of bits of range
> before extending.
> bits<2> opExtentAlign = 0;
> - let TSFlags{33-32} = opExtentAlign; // Alignment exponent before
> extending.
> + let TSFlags{34-33} = opExtentAlign; // Alignment exponent before
> extending.
>
> // If an instruction is valid on a subtarget, set the corresponding
> // bit from validSubTargets.
> // By default, instruction is valid on all subtargets.
> SubTarget validSubTargets = HasAnySubT;
> - let TSFlags{39-34} = validSubTargets.Value;
> + let TSFlags{40-35} = validSubTargets.Value;
>
> // Addressing mode for load/store instructions.
> AddrModeType addrMode = NoAddrMode;
> - let TSFlags{42-40} = addrMode.Value;
> + let TSFlags{43-41} = addrMode.Value;
>
> // Memory access size for mem access instructions (load/store)
> MemAccessSize accessSize = NoMemAccess;
> - let TSFlags{46-43} = accessSize.Value;
> + let TSFlags{47-44} = accessSize.Value;
>
> bits<1> isTaken = 0;
> - let TSFlags {47} = isTaken; // Branch prediction.
> + let TSFlags {48} = isTaken; // Branch prediction.
>
> bits<1> isFP = 0;
> - let TSFlags {48} = isFP; // Floating-point.
> + let TSFlags {49} = isFP; // Floating-point.
>
> bits<1> hasNewValue2 = 0;
> - let TSFlags{50} = hasNewValue2; // Second New-value producer insn.
> + let TSFlags{51} = hasNewValue2; // Second New-value producer insn.
> bits<3> opNewValue2 = 0;
> - let TSFlags{53-51} = opNewValue2; // Second New-value produced
> operand.
> + let TSFlags{54-52} = opNewValue2; // Second New-value produced
> operand.
>
> bits<1> isAccumulator = 0;
> - let TSFlags{54} = isAccumulator;
> + let TSFlags{55} = isAccumulator;
>
> bit cofMax1 = 0;
> let TSFlags{60} = cofMax1;
> @@ -200,6 +200,7 @@ class InstHexagon<dag outs, dag ins, str
> let NValueST = !if(isNVStore, "true", "false");
> let isNT = !if(isNonTemporal, "true", "false");
>
> + let hasSideEffects = 0;
> // *** Must match MCTargetDesc/HexagonBaseInfo.h ***
> }
>
>
> Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrFormatsV4.td
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrFormatsV4.td?rev=294226&r1=294225&r2=294226&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/HexagonInstrFormatsV4.td (original)
> +++ llvm/trunk/lib/Target/Hexagon/HexagonInstrFormatsV4.td Mon Feb
> 6 13:35:46 2017
> @@ -18,7 +18,7 @@
> //----------------------------------------------------------------------------//
>
> def TypeV4LDST : IType<9>;
> -def TypeNV : IType<10>;
> +def TypeNCJ : IType<10>;
> def TypeDUPLEX : IType<11>;
> def TypeCJ : IType<12>;
> def TypeEXTENDER : IType<30>;
> @@ -61,7 +61,7 @@ class InstDuplex<bits<4> iClass, list<da
>
> // *** Must match MCTargetDesc/HexagonBaseInfo.h ***
>
> - let TSFlags{4-0} = Type.Value;
> + let TSFlags{5-0} = Type.Value;
>
> // Predicated instructions.
> bits<1> isPredicated = 0;
> @@ -107,7 +107,7 @@ class InstDuplex<bits<4> iClass, list<da
> //
> class NVInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
> string cstr = "", InstrItinClass itin =
> NCJ_tc_3or4stall_SLOT0>
> - : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeNV>,
> OpcodeHexagon;
> + : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeNCJ>,
> OpcodeHexagon;
>
> class NVInst_V4<dag outs, dag ins, string asmstr, list<dag> pattern
> = [],
> string cstr = "", InstrItinClass itin =
> NCJ_tc_3or4stall_SLOT0>
>
> Modified:
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp?rev=294226&r1=294225&r2=294226&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
> (original)
> +++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
> Mon Feb 6 13:35:46 2017
> @@ -9,10 +9,10 @@
>
> #include "Hexagon.h"
> #include "HexagonFixupKinds.h"
> -#include "HexagonMCTargetDesc.h"
> #include "MCTargetDesc/HexagonBaseInfo.h"
> #include "MCTargetDesc/HexagonMCChecker.h"
> #include "MCTargetDesc/HexagonMCCodeEmitter.h"
> +#include "MCTargetDesc/HexagonMCTargetDesc.h"
> #include "MCTargetDesc/HexagonMCInstrInfo.h"
> #include "MCTargetDesc/HexagonMCShuffler.h"
> #include "llvm/MC/MCAsmBackend.h"
> @@ -59,9 +59,10 @@ class HexagonAsmBackend : public MCAsmBa
> RF.getFixups() = Fixups;
> }
> public:
> - HexagonAsmBackend(const Target &T, uint8_t OSABI, StringRef CPU) :
> - OSABI(OSABI), MCII (T.createMCInstrInfo()), RelaxTarget(new
> MCInst *),
> - Extender(nullptr) {}
> + HexagonAsmBackend(const Target &T, const Triple &TT, uint8_t OSABI,
> + StringRef CPU) :
> + OSABI(OSABI), CPU(CPU), MCII(T.createMCInstrInfo()),
> + RelaxTarget(new MCInst *), Extender(nullptr) {}
>
> MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const
> override {
> return createHexagonELFObjectWriter(OS, OSABI, CPU);
> @@ -88,101 +89,101 @@ public:
> // This table *must* be in same the order of fixup_* kinds in
> // HexagonFixupKinds.h.
> //
> - // namei offset bits flags
> - { "fixup_Hexagon_B22_PCREL", 0, 32,
> MCFixupKindInfo::FKF_IsPCRel },
> - { "fixup_Hexagon_B15_PCREL", 0, 32,
> MCFixupKindInfo::FKF_IsPCRel },
> - { "fixup_Hexagon_B7_PCREL", 0, 32,
> MCFixupKindInfo::FKF_IsPCRel },
> - { "fixup_Hexagon_LO16", 0, 32, 0 },
> - { "fixup_Hexagon_HI16", 0, 32, 0 },
> - { "fixup_Hexagon_32", 0, 32, 0 },
> - { "fixup_Hexagon_16", 0, 32, 0 },
> - { "fixup_Hexagon_8", 0, 32, 0 },
> - { "fixup_Hexagon_GPREL16_0", 0, 32, 0 },
> - { "fixup_Hexagon_GPREL16_1", 0, 32, 0 },
> - { "fixup_Hexagon_GPREL16_2", 0, 32, 0 },
> - { "fixup_Hexagon_GPREL16_3", 0, 32, 0 },
> - { "fixup_Hexagon_HL16", 0, 32, 0 },
> - { "fixup_Hexagon_B13_PCREL", 0, 32,
> MCFixupKindInfo::FKF_IsPCRel },
> - { "fixup_Hexagon_B9_PCREL", 0, 32,
> MCFixupKindInfo::FKF_IsPCRel },
> - { "fixup_Hexagon_B32_PCREL_X", 0, 32,
> MCFixupKindInfo::FKF_IsPCRel },
> - { "fixup_Hexagon_32_6_X", 0, 32, 0 },
> - { "fixup_Hexagon_B22_PCREL_X", 0, 32,
> MCFixupKindInfo::FKF_IsPCRel },
> - { "fixup_Hexagon_B15_PCREL_X", 0, 32,
> MCFixupKindInfo::FKF_IsPCRel },
> - { "fixup_Hexagon_B13_PCREL_X", 0, 32,
> MCFixupKindInfo::FKF_IsPCRel },
> - { "fixup_Hexagon_B9_PCREL_X", 0, 32,
> MCFixupKindInfo::FKF_IsPCRel },
> - { "fixup_Hexagon_B7_PCREL_X", 0, 32,
> MCFixupKindInfo::FKF_IsPCRel },
> - { "fixup_Hexagon_16_X", 0, 32, 0 },
> - { "fixup_Hexagon_12_X", 0, 32, 0 },
> - { "fixup_Hexagon_11_X", 0, 32, 0 },
> - { "fixup_Hexagon_10_X", 0, 32, 0 },
> - { "fixup_Hexagon_9_X", 0, 32, 0 },
> - { "fixup_Hexagon_8_X", 0, 32, 0 },
> - { "fixup_Hexagon_7_X", 0, 32, 0 },
> - { "fixup_Hexagon_6_X", 0, 32, 0 },
> - { "fixup_Hexagon_32_PCREL", 0, 32,
> MCFixupKindInfo::FKF_IsPCRel },
> - { "fixup_Hexagon_COPY", 0, 32, 0 },
> - { "fixup_Hexagon_GLOB_DAT", 0, 32, 0 },
> - { "fixup_Hexagon_JMP_SLOT", 0, 32, 0 },
> - { "fixup_Hexagon_RELATIVE", 0, 32, 0 },
> - { "fixup_Hexagon_PLT_B22_PCREL", 0, 32,
> MCFixupKindInfo::FKF_IsPCRel },
> - { "fixup_Hexagon_GOTREL_LO16", 0, 32, 0 },
> - { "fixup_Hexagon_GOTREL_HI16", 0, 32, 0 },
> - { "fixup_Hexagon_GOTREL_32", 0, 32, 0 },
> - { "fixup_Hexagon_GOT_LO16", 0, 32, 0 },
> - { "fixup_Hexagon_GOT_HI16", 0, 32, 0 },
> - { "fixup_Hexagon_GOT_32", 0, 32, 0 },
> - { "fixup_Hexagon_GOT_16", 0, 32, 0 },
> - { "fixup_Hexagon_DTPMOD_32", 0, 32, 0 },
> - { "fixup_Hexagon_DTPREL_LO16", 0, 32, 0 },
> - { "fixup_Hexagon_DTPREL_HI16", 0, 32, 0 },
> - { "fixup_Hexagon_DTPREL_32", 0, 32, 0 },
> - { "fixup_Hexagon_DTPREL_16", 0, 32, 0 },
> - { "fixup_Hexagon_GD_PLT_B22_PCREL", 0, 32,
> MCFixupKindInfo::FKF_IsPCRel },
> - { "fixup_Hexagon_LD_PLT_B22_PCREL", 0, 32,
> MCFixupKindInfo::FKF_IsPCRel },
> - { "fixup_Hexagon_GD_GOT_LO16", 0, 32, 0 },
> - { "fixup_Hexagon_GD_GOT_HI16", 0, 32, 0 },
> - { "fixup_Hexagon_GD_GOT_32", 0, 32, 0 },
> - { "fixup_Hexagon_GD_GOT_16", 0, 32, 0 },
> - { "fixup_Hexagon_LD_GOT_LO16", 0, 32, 0 },
> - { "fixup_Hexagon_LD_GOT_HI16", 0, 32, 0 },
> - { "fixup_Hexagon_LD_GOT_32", 0, 32, 0 },
> - { "fixup_Hexagon_LD_GOT_16", 0, 32, 0 },
> - { "fixup_Hexagon_IE_LO16", 0, 32, 0 },
> - { "fixup_Hexagon_IE_HI16", 0, 32, 0 },
> - { "fixup_Hexagon_IE_32", 0, 32, 0 },
> - { "fixup_Hexagon_IE_16", 0, 32, 0 },
> - { "fixup_Hexagon_IE_GOT_LO16", 0, 32, 0 },
> - { "fixup_Hexagon_IE_GOT_HI16", 0, 32, 0 },
> - { "fixup_Hexagon_IE_GOT_32", 0, 32, 0 },
> - { "fixup_Hexagon_IE_GOT_16", 0, 32, 0 },
> - { "fixup_Hexagon_TPREL_LO16", 0, 32, 0 },
> - { "fixup_Hexagon_TPREL_HI16", 0, 32, 0 },
> - { "fixup_Hexagon_TPREL_32", 0, 32, 0 },
> - { "fixup_Hexagon_TPREL_16", 0, 32, 0 },
> - { "fixup_Hexagon_6_PCREL_X", 0, 32,
> MCFixupKindInfo::FKF_IsPCRel },
> - { "fixup_Hexagon_GOTREL_32_6_X", 0, 32, 0 },
> - { "fixup_Hexagon_GOTREL_16_X", 0, 32, 0 },
> - { "fixup_Hexagon_GOTREL_11_X", 0, 32, 0 },
> - { "fixup_Hexagon_GOT_32_6_X", 0, 32, 0 },
> - { "fixup_Hexagon_GOT_16_X", 0, 32, 0 },
> - { "fixup_Hexagon_GOT_11_X", 0, 32, 0 },
> - { "fixup_Hexagon_DTPREL_32_6_X", 0, 32, 0 },
> - { "fixup_Hexagon_DTPREL_16_X", 0, 32, 0 },
> - { "fixup_Hexagon_DTPREL_11_X", 0, 32, 0 },
> - { "fixup_Hexagon_GD_GOT_32_6_X", 0, 32, 0 },
> - { "fixup_Hexagon_GD_GOT_16_X", 0, 32, 0 },
> - { "fixup_Hexagon_GD_GOT_11_X", 0, 32, 0 },
> - { "fixup_Hexagon_LD_GOT_32_6_X", 0, 32, 0 },
> - { "fixup_Hexagon_LD_GOT_16_X", 0, 32, 0 },
> - { "fixup_Hexagon_LD_GOT_11_X", 0, 32, 0 },
> - { "fixup_Hexagon_IE_32_6_X", 0, 32, 0 },
> - { "fixup_Hexagon_IE_16_X", 0, 32, 0 },
> - { "fixup_Hexagon_IE_GOT_32_6_X", 0, 32, 0 },
> - { "fixup_Hexagon_IE_GOT_16_X", 0, 32, 0 },
> - { "fixup_Hexagon_IE_GOT_11_X", 0, 32, 0 },
> - { "fixup_Hexagon_TPREL_32_6_X", 0, 32, 0 },
> - { "fixup_Hexagon_TPREL_16_X", 0, 32, 0 },
> - { "fixup_Hexagon_TPREL_11_X", 0, 32, 0 }
> + // namei offset bits flags
> + { "fixup_Hexagon_B22_PCREL", 0, 32,
> MCFixupKindInfo::FKF_IsPCRel },
> + { "fixup_Hexagon_B15_PCREL", 0, 32,
> MCFixupKindInfo::FKF_IsPCRel },
> + { "fixup_Hexagon_B7_PCREL", 0, 32,
> MCFixupKindInfo::FKF_IsPCRel },
> + { "fixup_Hexagon_LO16", 0, 32, 0 },
> + { "fixup_Hexagon_HI16", 0, 32, 0 },
> + { "fixup_Hexagon_32", 0, 32, 0 },
> + { "fixup_Hexagon_16", 0, 32, 0 },
> + { "fixup_Hexagon_8", 0, 32, 0 },
> + { "fixup_Hexagon_GPREL16_0", 0, 32, 0 },
> + { "fixup_Hexagon_GPREL16_1", 0, 32, 0 },
> + { "fixup_Hexagon_GPREL16_2", 0, 32, 0 },
> + { "fixup_Hexagon_GPREL16_3", 0, 32, 0 },
> + { "fixup_Hexagon_HL16", 0, 32, 0 },
> + { "fixup_Hexagon_B13_PCREL", 0, 32,
> MCFixupKindInfo::FKF_IsPCRel },
> + { "fixup_Hexagon_B9_PCREL", 0, 32,
> MCFixupKindInfo::FKF_IsPCRel },
> + { "fixup_Hexagon_B32_PCREL_X", 0, 32,
> MCFixupKindInfo::FKF_IsPCRel },
> + { "fixup_Hexagon_32_6_X", 0, 32, 0 },
> + { "fixup_Hexagon_B22_PCREL_X", 0, 32,
> MCFixupKindInfo::FKF_IsPCRel },
> + { "fixup_Hexagon_B15_PCREL_X", 0, 32,
> MCFixupKindInfo::FKF_IsPCRel },
> + { "fixup_Hexagon_B13_PCREL_X", 0, 32,
> MCFixupKindInfo::FKF_IsPCRel },
> + { "fixup_Hexagon_B9_PCREL_X", 0, 32,
> MCFixupKindInfo::FKF_IsPCRel },
> + { "fixup_Hexagon_B7_PCREL_X", 0, 32,
> MCFixupKindInfo::FKF_IsPCRel },
> + { "fixup_Hexagon_16_X", 0, 32, 0 },
> + { "fixup_Hexagon_12_X", 0, 32, 0 },
> + { "fixup_Hexagon_11_X", 0, 32, 0 },
> + { "fixup_Hexagon_10_X", 0, 32, 0 },
> + { "fixup_Hexagon_9_X", 0, 32, 0 },
> + { "fixup_Hexagon_8_X", 0, 32, 0 },
> + { "fixup_Hexagon_7_X", 0, 32, 0 },
> + { "fixup_Hexagon_6_X", 0, 32, 0 },
> + { "fixup_Hexagon_32_PCREL", 0, 32,
> MCFixupKindInfo::FKF_IsPCRel },
> + { "fixup_Hexagon_COPY", 0, 32, 0 },
> + { "fixup_Hexagon_GLOB_DAT", 0, 32, 0 },
> + { "fixup_Hexagon_JMP_SLOT", 0, 32, 0 },
> + { "fixup_Hexagon_RELATIVE", 0, 32, 0 },
> + { "fixup_Hexagon_PLT_B22_PCREL", 0, 32,
> MCFixupKindInfo::FKF_IsPCRel },
> + { "fixup_Hexagon_GOTREL_LO16", 0, 32, 0 },
> + { "fixup_Hexagon_GOTREL_HI16", 0, 32, 0 },
> + { "fixup_Hexagon_GOTREL_32", 0, 32, 0 },
> + { "fixup_Hexagon_GOT_LO16", 0, 32, 0 },
> + { "fixup_Hexagon_GOT_HI16", 0, 32, 0 },
> + { "fixup_Hexagon_GOT_32", 0, 32, 0 },
> + { "fixup_Hexagon_GOT_16", 0, 32, 0 },
> + { "fixup_Hexagon_DTPMOD_32", 0, 32, 0 },
> + { "fixup_Hexagon_DTPREL_LO16", 0, 32, 0 },
> + { "fixup_Hexagon_DTPREL_HI16", 0, 32, 0 },
> + { "fixup_Hexagon_DTPREL_32", 0, 32, 0 },
> + { "fixup_Hexagon_DTPREL_16", 0, 32, 0 },
> + { "fixup_Hexagon_GD_PLT_B22_PCREL",0, 32,
> MCFixupKindInfo::FKF_IsPCRel },
> + { "fixup_Hexagon_LD_PLT_B22_PCREL",0, 32,
> MCFixupKindInfo::FKF_IsPCRel },
> + { "fixup_Hexagon_GD_GOT_LO16", 0, 32, 0 },
> + { "fixup_Hexagon_GD_GOT_HI16", 0, 32, 0 },
> + { "fixup_Hexagon_GD_GOT_32", 0, 32, 0 },
> + { "fixup_Hexagon_GD_GOT_16", 0, 32, 0 },
> + { "fixup_Hexagon_LD_GOT_LO16", 0, 32, 0 },
> + { "fixup_Hexagon_LD_GOT_HI16", 0, 32, 0 },
> + { "fixup_Hexagon_LD_GOT_32", 0, 32, 0 },
> + { "fixup_Hexagon_LD_GOT_16", 0, 32, 0 },
> + { "fixup_Hexagon_IE_LO16", 0, 32, 0 },
> + { "fixup_Hexagon_IE_HI16", 0, 32, 0 },
> + { "fixup_Hexagon_IE_32", 0, 32, 0 },
> + { "fixup_Hexagon_IE_16", 0, 32, 0 },
> + { "fixup_Hexagon_IE_GOT_LO16", 0, 32, 0 },
> + { "fixup_Hexagon_IE_GOT_HI16", 0, 32, 0 },
> + { "fixup_Hexagon_IE_GOT_32", 0, 32, 0 },
> + { "fixup_Hexagon_IE_GOT_16", 0, 32, 0 },
> + { "fixup_Hexagon_TPREL_LO16", 0, 32, 0 },
> + { "fixup_Hexagon_TPREL_HI16", 0, 32, 0 },
> + { "fixup_Hexagon_TPREL_32", 0, 32, 0 },
> + { "fixup_Hexagon_TPREL_16", 0, 32, 0 },
> + { "fixup_Hexagon_6_PCREL_X", 0, 32,
> MCFixupKindInfo::FKF_IsPCRel },
> + { "fixup_Hexagon_GOTREL_32_6_X", 0, 32, 0 },
> + { "fixup_Hexagon_GOTREL_16_X", 0, 32, 0 },
> + { "fixup_Hexagon_GOTREL_11_X", 0, 32, 0 },
> + { "fixup_Hexagon_GOT_32_6_X", 0, 32, 0 },
> + { "fixup_Hexagon_GOT_16_X", 0, 32, 0 },
> + { "fixup_Hexagon_GOT_11_X", 0, 32, 0 },
> + { "fixup_Hexagon_DTPREL_32_6_X", 0, 32, 0 },
> + { "fixup_Hexagon_DTPREL_16_X", 0, 32, 0 },
> + { "fixup_Hexagon_DTPREL_11_X", 0, 32, 0 },
> + { "fixup_Hexagon_GD_GOT_32_6_X", 0, 32, 0 },
> + { "fixup_Hexagon_GD_GOT_16_X", 0, 32, 0 },
> + { "fixup_Hexagon_GD_GOT_11_X", 0, 32, 0 },
> + { "fixup_Hexagon_LD_GOT_32_6_X", 0, 32, 0 },
> + { "fixup_Hexagon_LD_GOT_16_X", 0, 32, 0 },
> + { "fixup_Hexagon_LD_GOT_11_X", 0, 32, 0 },
> + { "fixup_Hexagon_IE_32_6_X", 0, 32, 0 },
> + { "fixup_Hexagon_IE_16_X", 0, 32, 0 },
> + { "fixup_Hexagon_IE_GOT_32_6_X", 0, 32, 0 },
> + { "fixup_Hexagon_IE_GOT_16_X", 0, 32, 0 },
> + { "fixup_Hexagon_IE_GOT_11_X", 0, 32, 0 },
> + { "fixup_Hexagon_TPREL_32_6_X", 0, 32, 0 },
> + { "fixup_Hexagon_TPREL_16_X", 0, 32, 0 },
> + { "fixup_Hexagon_TPREL_11_X", 0, 32, 0 }
> };
>
> if (Kind < FirstTargetFixupKind)
> @@ -526,7 +527,7 @@ public:
> if (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) ==
> HexagonII::TypeJ ||
> (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) ==
> HexagonII::TypeCJ &&
> MCID.isBranch()) ||
> - (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) ==
> HexagonII::TypeNV &&
> + (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) ==
> HexagonII::TypeNCJ &&
> MCID.isBranch()) ||
> (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) ==
> HexagonII::TypeCR &&
> HMI.getOpcode() != Hexagon::C4_addipc))
> @@ -723,7 +724,8 @@ public:
> Size = 0;
> }
> }
> - bool Error = HexagonMCShuffle(*MCII,
> RF.getSubtargetInfo(), Inst);
> + bool Error = HexagonMCShuffle(true, *MCII,
> RF.getSubtargetInfo(),
> + Inst);
> //assert(!Error);
> (void)Error;
> ReplaceInstruction(Asm.getEmitter(), RF, Inst);
> @@ -738,15 +740,17 @@ public:
> }
> }
> }
> -};
> -} // end anonymous namespace
> +}; // class HexagonAsmBackend
>
> -namespace llvm {
> -MCAsmBackend *createHexagonAsmBackend(Target const &T,
> +} // namespace
> +
> +// MCAsmBackend
> +MCAsmBackend *llvm::createHexagonAsmBackend(Target const &T,
> MCRegisterInfo const & /*MRI*/,
> const Triple &TT, StringRef CPU,
> const MCTargetOptions &Options) {
> uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
> - return new HexagonAsmBackend(T, OSABI, CPU);
> -}
> +
> + StringRef CPUString = Hexagon_MC::selectHexagonCPU(TT, CPU);
> + return new HexagonAsmBackend(T, TT, OSABI, CPUString);
> }
>
> Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h?rev=294226&r1=294225&r2=294226&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h
> (original)
> +++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h Mon
> Feb 6 13:35:46 2017
> @@ -42,7 +42,7 @@ namespace HexagonII {
> TypeSYSTEM = 7,
> TypeXTYPE = 8,
> TypeV4LDST = 9,
> - TypeNV = 10,
> + TypeNCJ = 10,
> TypeDUPLEX = 11,
> TypeCJ = 12,
> TypeCVI_FIRST = 13,
> @@ -68,16 +68,10 @@ namespace HexagonII {
> };
>
> enum SubTarget {
> - HasV2SubT = 0xf,
> - HasV2SubTOnly = 0x1,
> - NoV2SubT = 0x0,
> - HasV3SubT = 0xe,
> - HasV3SubTOnly = 0x2,
> - NoV3SubT = 0x1,
> - HasV4SubT = 0xc,
> - NoV4SubT = 0x3,
> - HasV5SubT = 0x8,
> - NoV5SubT = 0x7
> + HasV4SubT = 0x3f,
> + HasV5SubT = 0x3e,
> + HasV55SubT = 0x3c,
> + HasV60SubT = 0x38,
> };
>
> enum AddrMode {
> @@ -107,102 +101,101 @@ namespace HexagonII {
> enum {
> // This 5-bit field describes the insn type.
> TypePos = 0,
> - TypeMask = 0x1f,
> + TypeMask = 0x3f,
>
> // Solo instructions.
> - SoloPos = 5,
> + SoloPos = 6,
> SoloMask = 0x1,
> // Packed only with A or X-type instructions.
> - SoloAXPos = 6,
> + SoloAXPos = 7,
> SoloAXMask = 0x1,
> // Only A-type instruction in first slot or nothing.
> - SoloAin1Pos = 7,
> + SoloAin1Pos = 8,
> SoloAin1Mask = 0x1,
>
> // Predicated instructions.
> - PredicatedPos = 8,
> + PredicatedPos = 9,
> PredicatedMask = 0x1,
> - PredicatedFalsePos = 9,
> + PredicatedFalsePos = 10,
> PredicatedFalseMask = 0x1,
> - PredicatedNewPos = 10,
> + PredicatedNewPos = 11,
> PredicatedNewMask = 0x1,
> - PredicateLatePos = 11,
> + PredicateLatePos = 12,
> PredicateLateMask = 0x1,
>
> // New-Value consumer instructions.
> - NewValuePos = 12,
> + NewValuePos = 13,
> NewValueMask = 0x1,
> // New-Value producer instructions.
> - hasNewValuePos = 13,
> + hasNewValuePos = 14,
> hasNewValueMask = 0x1,
> // Which operand consumes or produces a new value.
> - NewValueOpPos = 14,
> + NewValueOpPos = 15,
> NewValueOpMask = 0x7,
> // Stores that can become new-value stores.
> - mayNVStorePos = 17,
> + mayNVStorePos = 18,
> mayNVStoreMask = 0x1,
> // New-value store instructions.
> - NVStorePos = 18,
> + NVStorePos = 19,
> NVStoreMask = 0x1,
> // Loads that can become current-value loads.
> - mayCVLoadPos = 19,
> + mayCVLoadPos = 20,
> mayCVLoadMask = 0x1,
> // Current-value load instructions.
> - CVLoadPos = 20,
> + CVLoadPos = 21,
> CVLoadMask = 0x1,
>
> // Extendable insns.
> - ExtendablePos = 21,
> + ExtendablePos = 22,
> ExtendableMask = 0x1,
> // Insns must be extended.
> - ExtendedPos = 22,
> + ExtendedPos = 23,
> ExtendedMask = 0x1,
> // Which operand may be extended.
> - ExtendableOpPos = 23,
> + ExtendableOpPos = 24,
> ExtendableOpMask = 0x7,
> // Signed or unsigned range.
> - ExtentSignedPos = 26,
> + ExtentSignedPos = 27,
> ExtentSignedMask = 0x1,
> // Number of bits of range before extending operand.
> - ExtentBitsPos = 27,
> + ExtentBitsPos = 28,
> ExtentBitsMask = 0x1f,
> // Alignment power-of-two before extending operand.
> - ExtentAlignPos = 32,
> + ExtentAlignPos = 33,
> ExtentAlignMask = 0x3,
>
> // Valid subtargets
> - validSubTargetPos = 34,
> - validSubTargetMask = 0xf,
> + validSubTargetPos = 35,
> + validSubTargetMask = 0x3f,
>
> // Addressing mode for load/store instructions.
> - AddrModePos = 40,
> + AddrModePos = 41,
> AddrModeMask = 0x7,
> // Access size for load/store instructions.
> - MemAccessSizePos = 43,
> + MemAccessSizePos = 44,
> MemAccesSizeMask = 0xf,
>
> // Branch predicted taken.
> - TakenPos = 47,
> + TakenPos = 48,
> TakenMask = 0x1,
>
> // Floating-point instructions.
> - FPPos = 48,
> + FPPos = 49,
> FPMask = 0x1,
>
> // New-Value producer-2 instructions.
> - hasNewValuePos2 = 50,
> + hasNewValuePos2 = 51,
> hasNewValueMask2 = 0x1,
> -
> // Which operand consumes or produces a new value.
> - NewValueOpPos2 = 51,
> + NewValueOpPos2 = 52,
> NewValueOpMask2 = 0x7,
>
> // Accumulator instructions.
> - AccumulatorPos = 54,
> + AccumulatorPos = 55,
> AccumulatorMask = 0x1,
>
> // Complex XU, prevent xu competition by preferring slot3
> - PrefersSlot3Pos = 55,
> + PrefersSlot3Pos = 56,
> PrefersSlot3Mask = 0x1,
>
> CofMax1Pos = 60,
> @@ -217,8 +210,6 @@ namespace HexagonII {
> // Hexagon Specific MachineOperand flags.
> MO_NO_FLAG,
>
> - HMOTF_ConstExtended = 1,
> -
> /// MO_PCREL - On a symbol operand, indicates a PC-relative
> relocation
> /// Used for computing a global address for PIC compilations
> MO_PCREL,
> @@ -250,7 +241,13 @@ namespace HexagonII {
>
> // MO_TPREL - indicates relocation for TLS
> // local Executable method
> - MO_TPREL
> + MO_TPREL,
> +
> + // HMOTF_ConstExtended
> + // Addendum to abovem, indicates a const extended op
> + // Can be used as a mask.
> + HMOTF_ConstExtended = 0x80
> +
> };
>
> // Hexagon Sub-instruction classes.
>
> Modified:
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp?rev=294226&r1=294225&r2=294226&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp
> (original)
> +++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp
> Mon Feb 6 13:35:46 2017
> @@ -23,6 +23,7 @@ HexagonMCAsmInfo::HexagonMCAsmInfo(const
> Data32bitsDirective = "\t.word\t";
> Data64bitsDirective = nullptr; // .xword is only supported by V9.
> CommentString = "//";
> + SupportsDebugInformation = true;
>
> LCOMMDirectiveAlignmentType = LCOMM::ByteAlignment;
> InlineAsmStart = "# InlineAsm Start";
> @@ -30,8 +31,8 @@ HexagonMCAsmInfo::HexagonMCAsmInfo(const
> ZeroDirective = "\t.space\t";
> AscizDirective = "\t.string\t";
>
> - SupportsDebugInformation = true;
> MinInstAlignment = 4;
> UsesELFSectionDirectiveForBSS = true;
> ExceptionsType = ExceptionHandling::DwarfCFI;
> + UseLogicalShr = false;
> }
>
> Modified:
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp?rev=294226&r1=294225&r2=294226&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp
> (original)
> +++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp
> Mon Feb 6 13:35:46 2017
> @@ -47,12 +47,40 @@ void HexagonMCChecker::init() {
> if (HexagonMCInstrInfo::isBundle(MCB))
> // Unfurl a bundle.
> for (auto const&I : HexagonMCInstrInfo::bundleInstructions(MCB)) {
> - init(*I.getInst());
> + MCInst const &Inst = *I.getInst();
> + if (HexagonMCInstrInfo::isDuplex(MCII, Inst)) {
> + init(*Inst.getOperand(0).getInst());
> + init(*Inst.getOperand(1).getInst());
> + }
> + else
> + init(Inst);
> }
> else
> init(MCB);
> }
>
> +void HexagonMCChecker::initReg(MCInst const &MCI, unsigned R,
> unsigned &PredReg,
> + bool &isTrue) {
> + if (HexagonMCInstrInfo::isPredicated(MCII, MCI) &&
> isPredicateRegister(R)) {
> + // Note an used predicate register.
> + PredReg = R;
> + isTrue = HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI);
> +
> + // Note use of new predicate register.
> + if (HexagonMCInstrInfo::isPredicatedNew(MCII, MCI))
> + NewPreds.insert(PredReg);
> + }
> + else
> + // Note register use. Super-registers are not tracked directly,
> + // but their components.
> + for(MCRegAliasIterator SRI(R, &RI, !MCSubRegIterator(R,
> &RI).isValid());
> + SRI.isValid();
> + ++SRI)
> + if (!MCSubRegIterator(*SRI, &RI).isValid())
> + // Skip super-registers used indirectly.
> + Uses.insert(*SRI);
> +}
> +
> void HexagonMCChecker::init(MCInst const& MCI) {
> const MCInstrDesc& MCID = HexagonMCInstrInfo::getDesc(MCII, MCI);
> unsigned PredReg = Hexagon::NoRegister;
> @@ -60,28 +88,10 @@ void HexagonMCChecker::init(MCInst const
>
> // Get used registers.
> for (unsigned i = MCID.getNumDefs(); i < MCID.getNumOperands(); ++i)
> - if (MCI.getOperand(i).isReg()) {
> - unsigned R = MCI.getOperand(i).getReg();
> -
> - if (HexagonMCInstrInfo::isPredicated(MCII, MCI) &&
> isPredicateRegister(R)) {
> - // Note an used predicate register.
> - PredReg = R;
> - isTrue = HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI);
> -
> - // Note use of new predicate register.
> - if (HexagonMCInstrInfo::isPredicatedNew(MCII, MCI))
> - NewPreds.insert(PredReg);
> - }
> - else
> - // Note register use. Super-registers are not tracked
> directly,
> - // but their components.
> - for(MCRegAliasIterator SRI(R, &RI, !MCSubRegIterator(R,
> &RI).isValid());
> - SRI.isValid();
> - ++SRI)
> - if (!MCSubRegIterator(*SRI, &RI).isValid())
> - // Skip super-registers used indirectly.
> - Uses.insert(*SRI);
> - }
> + if (MCI.getOperand(i).isReg())
> + initReg(MCI, MCI.getOperand(i).getReg(), PredReg, isTrue);
> + for (unsigned i = 0; i < MCID.getNumImplicitUses(); ++i)
> + initReg(MCI, MCID.getImplicitUses()[i], PredReg, isTrue);
>
> // Get implicit register definitions.
> if (const MCPhysReg *ImpDef = MCID.getImplicitDefs())
> @@ -216,9 +226,11 @@ void HexagonMCChecker::init(MCInst const
> if (!MCSubRegIterator(N, &RI).isValid()) {
> // Super-registers cannot use new values.
> if (MCID.isBranch())
> - NewUses[N] =
> NewSense::Jmp(llvm::HexagonMCInstrInfo::getType(MCII, MCI) ==
> HexagonII::TypeNV);
> + NewUses[N] = NewSense::Jmp(
> + llvm::HexagonMCInstrInfo::getType(MCII, MCI) ==
> HexagonII::TypeNCJ);
> else
> - NewUses[N] = NewSense::Use(PredReg,
> HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI));
> + NewUses[N] = NewSense::Use(
> + PredReg, HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI));
> }
> }
> }
> @@ -230,14 +242,18 @@ HexagonMCChecker::HexagonMCChecker(MCIns
> init();
> }
>
> -bool HexagonMCChecker::check() {
> +bool HexagonMCChecker::check(bool FullCheck) {
> bool chkB = checkBranches();
> bool chkP = checkPredicates();
> bool chkNV = checkNewValues();
> bool chkR = checkRegisters();
> bool chkS = checkSolo();
> - bool chkSh = checkShuffle();
> - bool chkSl = checkSlots();
> + bool chkSh = true;
> + if (FullCheck)
> + chkSh = checkShuffle();
> + bool chkSl = true;
> + if (FullCheck)
> + chkSl = checkSlots();
> bool chk = chkB && chkP && chkNV && chkR && chkS && chkSh && chkSl;
>
> return chk;
> @@ -504,7 +520,7 @@ bool HexagonMCChecker::checkShuffle() {
> HexagonMCErrInfo errInfo;
> // Branch info is lost when duplexing. The unduplexed insns must be
> // checked and only branch errors matter for this case.
> - HexagonMCShuffler MCS(MCII, STI, MCB);
> + HexagonMCShuffler MCS(true, MCII, STI, MCB);
> if (!MCS.check()) {
> if (MCS.getError() == HexagonShuffler::SHUFFLE_ERROR_BRANCHES) {
> errInfo.setError(HexagonMCErrInfo::CHECK_ERROR_SHUFFLE);
> @@ -513,7 +529,7 @@ bool HexagonMCChecker::checkShuffle() {
> return false;
> }
> }
> - HexagonMCShuffler MCSDX(MCII, STI, MCBDX);
> + HexagonMCShuffler MCSDX(true, MCII, STI, MCBDX);
> if (!MCSDX.check()) {
> errInfo.setError(HexagonMCErrInfo::CHECK_ERROR_SHUFFLE);
> errInfo.setShuffleError(MCSDX.getError());
>
> Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h?rev=294226&r1=294225&r2=294226&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h
> (original)
> +++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h
> Mon Feb 6 13:35:46 2017
> @@ -168,6 +168,7 @@ class HexagonMCChecker {
>
> void init();
> void init(MCInst const&);
> + void initReg(MCInst const &, unsigned, unsigned &PredReg, bool
> &isTrue);
>
> // Checks performed.
> bool checkBranches();
> @@ -177,6 +178,7 @@ class HexagonMCChecker {
> bool checkSolo();
> bool checkShuffle();
> bool checkSlots();
> + bool checkSize();
>
> static void compoundRegisterMap(unsigned&);
>
> @@ -196,7 +198,7 @@ class HexagonMCChecker {
> explicit HexagonMCChecker(MCInstrInfo const &MCII,
> MCSubtargetInfo const &STI, MCInst& mcb, MCInst &mcbdx,
> const MCRegisterInfo& ri);
>
> - bool check();
> + bool check(bool FullCheck = true);
>
> /// add a new error/warning
> void addErrInfo(HexagonMCErrInfo &err) { ErrInfoQ.push(err.s); };
>
> Modified:
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp?rev=294226&r1=294225&r2=294226&view=diff
> ==============================================================================
> ---
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
> (original)
> +++
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
> Mon Feb 6 13:35:46 2017
> @@ -65,9 +65,10 @@ uint32_t HexagonMCCodeEmitter::parseBits
> return HexagonII::INST_PARSE_NOT_END;
> }
>
> -void HexagonMCCodeEmitter::encodeInstruction(MCInst const &MI,
> raw_ostream &OS,
> +/// EncodeInstruction - Emit the bundle
> +void HexagonMCCodeEmitter::encodeInstruction(const MCInst &MI,
> raw_ostream &OS,
>
> SmallVectorImpl<MCFixup> &Fixups,
> - MCSubtargetInfo const
> &STI) const {
> + const MCSubtargetInfo
> &STI) const {
> MCInst &HMB = const_cast<MCInst &>(MI);
>
> assert(HexagonMCInstrInfo::isBundle(HMB));
> @@ -137,60 +138,7 @@ void HexagonMCCodeEmitter::EncodeSingleI
> MI.getOpcode() <= Hexagon::DuplexIClassF) {
> assert(Parse == HexagonII::INST_PARSE_DUPLEX &&
> "Emitting duplex without duplex parse bits");
> - unsigned dupIClass;
> - switch (MI.getOpcode()) {
> - case Hexagon::DuplexIClass0:
> - dupIClass = 0;
> - break;
> - case Hexagon::DuplexIClass1:
> - dupIClass = 1;
> - break;
> - case Hexagon::DuplexIClass2:
> - dupIClass = 2;
> - break;
> - case Hexagon::DuplexIClass3:
> - dupIClass = 3;
> - break;
> - case Hexagon::DuplexIClass4:
> - dupIClass = 4;
> - break;
> - case Hexagon::DuplexIClass5:
> - dupIClass = 5;
> - break;
> - case Hexagon::DuplexIClass6:
> - dupIClass = 6;
> - break;
> - case Hexagon::DuplexIClass7:
> - dupIClass = 7;
> - break;
> - case Hexagon::DuplexIClass8:
> - dupIClass = 8;
> - break;
> - case Hexagon::DuplexIClass9:
> - dupIClass = 9;
> - break;
> - case Hexagon::DuplexIClassA:
> - dupIClass = 10;
> - break;
> - case Hexagon::DuplexIClassB:
> - dupIClass = 11;
> - break;
> - case Hexagon::DuplexIClassC:
> - dupIClass = 12;
> - break;
> - case Hexagon::DuplexIClassD:
> - dupIClass = 13;
> - break;
> - case Hexagon::DuplexIClassE:
> - dupIClass = 14;
> - break;
> - case Hexagon::DuplexIClassF:
> - dupIClass = 15;
> - break;
> - default:
> - llvm_unreachable("Unimplemented DuplexIClass");
> - break;
> - }
> + unsigned dupIClass = MI.getOpcode() - Hexagon::DuplexIClass0;
> // 29 is the bit position.
> // 0b1110 =0xE bits are masked off and down shifted by 1 bit.
> // Last bit is moved to bit position 13
> @@ -390,7 +338,8 @@ unsigned HexagonMCCodeEmitter::getExprOp
> int64_t Value;
> if (ME->evaluateAsAbsolute(Value))
> return Value;
> - assert(ME->getKind() == MCExpr::SymbolRef || ME->getKind() ==
> MCExpr::Binary);
> + assert(ME->getKind() == MCExpr::SymbolRef ||
> + ME->getKind() == MCExpr::Binary);
> if (ME->getKind() == MCExpr::Binary) {
> MCBinaryExpr const *Binary = cast<MCBinaryExpr>(ME);
> getExprOpValue(MI, MO, Binary->getLHS(), Fixups, STI);
> @@ -523,7 +472,7 @@ unsigned HexagonMCCodeEmitter::getExprOp
> else
> if (MCID.mayStore() || MCID.mayLoad()) {
> for (const MCPhysReg *ImpUses = MCID.getImplicitUses();
> *ImpUses;
> - ++ImpUses) {
> + ++ImpUses) {
> if (*ImpUses != Hexagon::GP)
> continue;
> switch (HexagonMCInstrInfo::getAccessSize(MCII, MI)) {
> @@ -543,8 +492,7 @@ unsigned HexagonMCCodeEmitter::getExprOp
> raise_relocation_error(bits, kind);
> }
> }
> - }
> - else
> + } else
> raise_relocation_error(bits, kind);
> break;
> }
> @@ -759,6 +707,13 @@ unsigned
> HexagonMCCodeEmitter::getMachineOpValue(MCInst const &MI, MCOperand
> const &MO,
> SmallVectorImpl<MCFixup>
> &Fixups,
> MCSubtargetInfo const &STI)
> const {
> + size_t OperandNumber = ~0U;
> + for (unsigned i = 0, n = MI.getNumOperands(); i < n; ++i)
> + if (&MI.getOperand(i) == &MO) {
> + OperandNumber = i;
> + break;
> + }
> + assert((OperandNumber != ~0U) && "Operand not found");
>
> if (HexagonMCInstrInfo::isNewValue(MCII, MI) &&
> &MO == &MI.getOperand(HexagonMCInstrInfo::getNewValueOp(MCII,
> MI))) {
>
> Modified:
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCCompound.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCCompound.cpp?rev=294226&r1=294225&r2=294226&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCCompound.cpp
> (original)
> +++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCCompound.cpp
> Mon Feb 6 13:35:46 2017
> @@ -14,6 +14,7 @@
> #include "Hexagon.h"
> #include "MCTargetDesc/HexagonBaseInfo.h"
> #include "MCTargetDesc/HexagonMCInstrInfo.h"
> +#include "MCTargetDesc/HexagonMCShuffler.h"
> #include "llvm/MC/MCContext.h"
> #include "llvm/MC/MCInst.h"
> #include "llvm/Support/Debug.h"
> @@ -396,7 +397,7 @@ static bool lookForCompound(MCInstrInfo
> /// is found update the contents fo the bundle with the compound insn.
> /// If a compound instruction is found then the bundle will have one
> /// additional slot.
> -void HexagonMCInstrInfo::tryCompound(MCInstrInfo const &MCII,
> +void HexagonMCInstrInfo::tryCompound(MCInstrInfo const &MCII,
> MCSubtargetInfo const &STI,
> MCContext &Context, MCInst &MCI) {
> assert(HexagonMCInstrInfo::isBundle(MCI) &&
> "Non-Bundle where Bundle expected");
> @@ -405,8 +406,23 @@ void HexagonMCInstrInfo::tryCompound(MCI
> if (MCI.size() < 2)
> return;
>
> + bool StartedValid = llvm::HexagonMCShuffle(false, MCII, STI, MCI);
> +
> + // Create a vector, needed to keep the order of jump instructions.
> + MCInst CheckList(MCI);
> +
> // Look for compounds until none are found, only update the
> bundle when
> // a compound is found.
> - while (lookForCompound(MCII, Context, MCI))
> - ;
> + while (lookForCompound(MCII, Context, CheckList)) {
> + // Keep the original bundle around in case the shuffle fails.
> + MCInst OriginalBundle(MCI);
> +
> + // Need to update the bundle.
> + MCI = CheckList;
> +
> + if (StartedValid && !llvm::HexagonMCShuffle(false, MCII, STI,
> MCI)) {
> + DEBUG(dbgs() << "Found ERROR\n");
> + MCI = OriginalBundle;
> + }
> + }
> }
>
> Modified:
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp?rev=294226&r1=294225&r2=294226&view=diff
> ==============================================================================
> ---
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp
> (original)
> +++
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp
> Mon Feb 6 13:35:46 2017
> @@ -15,6 +15,7 @@
> #include "MCTargetDesc/HexagonMCInstrInfo.h"
>
> #include "llvm/ADT/SmallVector.h"
> +#include "llvm/MC/MCSubtargetInfo.h"
> #include "llvm/Support/Debug.h"
> #include "llvm/Support/raw_ostream.h"
>
> @@ -262,6 +263,7 @@ unsigned HexagonMCInstrInfo::getDuplexCa
> case Hexagon::EH_RETURN_JMPR:
>
> case Hexagon::J2_jumpr:
> + case Hexagon::PS_jmpret:
> // jumpr r31
> // Actual form JMPR %PC<imp-def>, %R31<imp-use>,
> %R0<imp-use,internal>.
> DstReg = MCI.getOperand(0).getReg();
> @@ -275,6 +277,12 @@ unsigned HexagonMCInstrInfo::getDuplexCa
> case Hexagon::J2_jumprfnew:
> case Hexagon::J2_jumprtnewpt:
> case Hexagon::J2_jumprfnewpt:
> + case Hexagon::PS_jmprett:
> + case Hexagon::PS_jmpretf:
> + case Hexagon::PS_jmprettnew:
> + case Hexagon::PS_jmpretfnew:
> + case Hexagon::PS_jmprettnewpt:
> + case Hexagon::PS_jmpretfnewpt:
> DstReg = MCI.getOperand(1).getReg();
> SrcReg = MCI.getOperand(0).getReg();
> // [if ([!]p0[.new])] jumpr r31
> @@ -284,15 +292,10 @@ unsigned HexagonMCInstrInfo::getDuplexCa
> }
> break;
> case Hexagon::L4_return_t:
> -
> case Hexagon::L4_return_f:
> -
> case Hexagon::L4_return_tnew_pnt:
> -
> case Hexagon::L4_return_fnew_pnt:
> -
> case Hexagon::L4_return_tnew_pt:
> -
> case Hexagon::L4_return_fnew_pt:
> // [if ([!]p0[.new])] dealloc_return
> SrcReg = MCI.getOperand(0).getReg();
> @@ -565,7 +568,8 @@ bool HexagonMCInstrInfo::subInstWouldBeE
> bool HexagonMCInstrInfo::isOrderedDuplexPair(MCInstrInfo const &MCII,
> MCInst const &MIa,
> bool ExtendedA,
> MCInst const &MIb,
> bool ExtendedB,
> - bool bisReversable) {
> + bool bisReversable,
> + MCSubtargetInfo const
> &STI) {
> // Slot 1 cannot be extended in duplexes PRM 10.5
> if (ExtendedA)
> return false;
> @@ -625,11 +629,16 @@ bool HexagonMCInstrInfo::isOrderedDuplex
> return false;
> }
>
> - // If a store appears, it must be in slot 0 (MIa) 1st, and then
> slot 1 (MIb);
> - // therefore, not duplexable if slot 1 is a store, and slot 0
> is not.
> - if ((MIbG == HexagonII::HSIG_S1) || (MIbG == HexagonII::HSIG_S2)) {
> - if ((MIaG != HexagonII::HSIG_S1) && (MIaG != HexagonII::HSIG_S2))
> - return false;
> + if (STI.getCPU().equals_lower("hexagonv4") ||
> + STI.getCPU().equals_lower("hexagonv5") ||
> + STI.getCPU().equals_lower("hexagonv55") ||
> + STI.getCPU().equals_lower("hexagonv60")) {
> + // If a store appears, it must be in slot 0 (MIa) 1st, and then
> slot 1 (MIb);
> + // therefore, not duplexable if slot 1 is a store, and slot 0
> is not.
> + if ((MIbG == HexagonII::HSIG_S1) || (MIbG == HexagonII::HSIG_S2)) {
> + if ((MIaG != HexagonII::HSIG_S1) && (MIaG != HexagonII::HSIG_S2))
> + return false;
> + }
> }
>
> return (isDuplexPairMatch(MIaG, MIbG));
> @@ -703,6 +712,7 @@ MCInst HexagonMCInstrInfo::deriveSubInst
> Result.setOpcode(Hexagon::SA1_dec);
> addOps(Result, Inst, 0);
> addOps(Result, Inst, 1);
> + addOps(Result, Inst, 2);
> break;
> } // 1,2 SUBInst $Rd = add($Rs,#-1)
> else if (Inst.getOperand(1).getReg() == Hexagon::R29) {
> @@ -806,20 +816,27 @@ MCInst HexagonMCInstrInfo::deriveSubInst
> break; // none SUBInst deallocframe
> case Hexagon::EH_RETURN_JMPR:
> case Hexagon::J2_jumpr:
> + case Hexagon::PS_jmpret:
> Result.setOpcode(Hexagon::SL2_jumpr31);
> break; // none SUBInst jumpr r31
> case Hexagon::J2_jumprf:
> + case Hexagon::PS_jmpretf:
> Result.setOpcode(Hexagon::SL2_jumpr31_f);
> break; // none SUBInst if (!p0) jumpr r31
> case Hexagon::J2_jumprfnew:
> case Hexagon::J2_jumprfnewpt:
> + case Hexagon::PS_jmpretfnewpt:
> + case Hexagon::PS_jmpretfnew:
> Result.setOpcode(Hexagon::SL2_jumpr31_fnew);
> break; // none SUBInst if (!p0.new) jumpr:nt r31
> case Hexagon::J2_jumprt:
> + case Hexagon::PS_jmprett:
> Result.setOpcode(Hexagon::SL2_jumpr31_t);
> break; // none SUBInst if (p0) jumpr r31
> case Hexagon::J2_jumprtnew:
> case Hexagon::J2_jumprtnewpt:
> + case Hexagon::PS_jmprettnewpt:
> + case Hexagon::PS_jmprettnew:
> Result.setOpcode(Hexagon::SL2_jumpr31_tnew);
> break; // none SUBInst if (p0.new) jumpr:nt r31
> case Hexagon::L2_loadrb_io:
> @@ -966,6 +983,7 @@ MCInst HexagonMCInstrInfo::deriveSubInst
> if (Absolute && Value == -1) {
> Result.setOpcode(Hexagon::SA1_setin1);
> addOps(Result, Inst, 0);
> + addOps(Result, Inst, 1);
> break; // 2 1 SUBInst $Rd = #-1
> } else {
> Result.setOpcode(Hexagon::SA1_seti);
> @@ -1005,6 +1023,7 @@ static bool isStoreInst(unsigned opCode)
>
> SmallVector<DuplexCandidate, 8>
> HexagonMCInstrInfo::getDuplexPossibilties(MCInstrInfo const &MCII,
> + MCSubtargetInfo const &STI,
> MCInst const &MCB) {
> assert(isBundle(MCB));
> SmallVector<DuplexCandidate, 8> duplexToTry;
> @@ -1033,7 +1052,7 @@ HexagonMCInstrInfo::getDuplexPossibiltie
> HexagonMCInstrInfo::hasExtenderForIndex(MCB, k - 1),
> *MCB.getOperand(j).getInst(),
> HexagonMCInstrInfo::hasExtenderForIndex(MCB, j - 1),
> - bisReversable)) {
> + bisReversable, STI)) {
> // Get iClass.
> unsigned iClass = iClassOfDuplexPair(
> getDuplexCandidateGroup(*MCB.getOperand(k).getInst()),
> @@ -1058,7 +1077,7 @@ HexagonMCInstrInfo::getDuplexPossibiltie
> HexagonMCInstrInfo::hasExtenderForIndex(MCB, j - 1),
> *MCB.getOperand(k).getInst(),
> HexagonMCInstrInfo::hasExtenderForIndex(MCB, k - 1),
> - bisReversable)) {
> + bisReversable, STI)) {
> // Get iClass.
> unsigned iClass = iClassOfDuplexPair(
> getDuplexCandidateGroup(*MCB.getOperand(j).getInst()),
>
> Modified:
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp?rev=294226&r1=294225&r2=294226&view=diff
> ==============================================================================
> ---
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp
> (original)
> +++
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp
> Mon Feb 6 13:35:46 2017
> @@ -37,30 +37,19 @@
>
> using namespace llvm;
>
> -static cl::opt<unsigned>
> - GPSize("gpsize", cl::NotHidden,
> - cl::desc("Global Pointer Addressing Size. The default
> size is 8."),
> - cl::Prefix, cl::init(8));
> +static cl::opt<unsigned> GPSize
> + ("gpsize", cl::NotHidden,
> + cl::desc("Global Pointer Addressing Size. The default size is 8."),
> + cl::Prefix,
> + cl::init(8));
>
> -void HexagonMCELFStreamer::EmitInstruction(const MCInst &MCK,
> +void HexagonMCELFStreamer::EmitInstruction(const MCInst &MCB,
> const MCSubtargetInfo
> &STI) {
> - MCInst HMI = HexagonMCInstrInfo::createBundle();
> - MCInst *MCB;
> -
> - if (MCK.getOpcode() != Hexagon::BUNDLE) {
> - HMI.addOperand(MCOperand::createInst(&MCK));
> - MCB = &HMI;
> - } else
> - MCB = const_cast<MCInst *>(&MCK);
> -
> - // Examines packet and pad the packet, if needed, when an
> - // end-loop is in the bundle.
> - HexagonMCInstrInfo::padEndloop(getContext(), *MCB);
> - HexagonMCShuffle(*MCII, STI, *MCB);
> -
> - assert(HexagonMCInstrInfo::bundleSize(*MCB) <= HEXAGON_PACKET_SIZE);
> + assert(MCB.getOpcode() == Hexagon::BUNDLE);
> + assert(HexagonMCInstrInfo::bundleSize(MCB) <= HEXAGON_PACKET_SIZE);
> + assert(HexagonMCInstrInfo::bundleSize(MCB) > 0);
> bool Extended = false;
> - for (auto &I : HexagonMCInstrInfo::bundleInstructions(*MCB)) {
> + for (auto &I : HexagonMCInstrInfo::bundleInstructions(MCB)) {
> MCInst *MCI = const_cast<MCInst *>(I.getInst());
> if (Extended) {
> if (HexagonMCInstrInfo::isDuplex(*MCII, *MCI)) {
> @@ -77,11 +66,12 @@ void HexagonMCELFStreamer::EmitInstructi
>
> // At this point, MCB is a bundle
> // Iterate through the bundle and assign addends for the instructions
> - for (auto const &I : HexagonMCInstrInfo::bundleInstructions(*MCB)) {
> + for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCB)) {
> MCInst *MCI = const_cast<MCInst *>(I.getInst());
> EmitSymbol(*MCI);
> }
> - MCObjectStreamer::EmitInstruction(*MCB, STI);
> +
> + MCObjectStreamer::EmitInstruction(MCB, STI);
> }
>
> void HexagonMCELFStreamer::EmitSymbol(const MCInst &Inst) {
> @@ -119,9 +109,11 @@ void HexagonMCELFStreamer::HexagonMCEmit
> MCSectionSubPair P = getCurrentSection();
> SwitchSection(&Section);
>
> - EmitValueToAlignment(ByteAlignment, 0, 1, 0);
> - EmitLabel(Symbol);
> - EmitZeros(Size);
> + if (ELFSymbol->isUndefined(false)) {
> + EmitValueToAlignment(ByteAlignment, 0, 1, 0);
> + EmitLabel(Symbol);
> + EmitZeros(Size);
> + }
>
> // Update the maximum alignment of the section if necessary.
> if (ByteAlignment > Section.getAlignment())
> @@ -144,9 +136,10 @@ void HexagonMCELFStreamer::HexagonMCEmit
> ELFSymbol->setSize(MCConstantExpr::create(Size, getContext()));
> }
>
> -void HexagonMCELFStreamer::HexagonMCEmitLocalCommonSymbol(
> - MCSymbol *Symbol, uint64_t Size, unsigned ByteAlignment,
> - unsigned AccessSize) {
> +void HexagonMCELFStreamer::HexagonMCEmitLocalCommonSymbol(MCSymbol
> *Symbol,
> + uint64_t Size,
> + unsigned
> ByteAlignment,
> + unsigned
> AccessSize) {
> getAssembler().registerSymbol(*Symbol);
> auto ELFSymbol = cast<MCSymbolELF>(Symbol);
> ELFSymbol->setBinding(ELF::STB_LOCAL);
> @@ -154,11 +147,12 @@ void HexagonMCELFStreamer::HexagonMCEmit
> HexagonMCEmitCommonSymbol(Symbol, Size, ByteAlignment, AccessSize);
> }
>
> -namespace llvm {
>
> -MCStreamer *createHexagonELFStreamer(MCContext &Context,
> MCAsmBackend &MAB,
> - raw_pwrite_stream &OS,
> MCCodeEmitter *CE) {
> - return new HexagonMCELFStreamer(Context, MAB, OS, CE);
> -}
> +namespace llvm {
> + MCStreamer *createHexagonELFStreamer(Triple const &TT, MCContext
> &Context,
> + MCAsmBackend &MAB,
> + raw_pwrite_stream &OS,
> MCCodeEmitter *CE) {
> + return new HexagonMCELFStreamer(Context, MAB, OS, CE);
> + }
>
> } // end namespace llvm
>
> Modified:
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.h?rev=294226&r1=294225&r2=294226&view=diff
> ==============================================================================
> ---
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.h
> (original)
> +++
> llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.h
> Mon Feb 6 13:35:46 2017
> @@ -27,6 +27,13 @@ public:
> : MCELFStreamer(Context, TAB, OS, Emitter),
> MCII(createHexagonMCInstrInfo()) {}
>
> + HexagonMC
>
--
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