[PATCH] D26855: New unsafe-fp-math implementation for X86 target

Simon Pilgrim via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Sun Feb 5 10:42:31 PST 2017

RKSimon added a comment.

In https://reviews.llvm.org/D26855#667181, @guyblank wrote:

> But I'm also concerned about other cpus for which we don't have an accurate scheduler model (broadwell, skylake), should these be excluded as well?

If the cpu is using an older scheduler model then its already not necessarily being optimally scheduled - I don't see this patch being any different.

Comment at: lib/Target/X86/X86InstrInfo.cpp:9686
+  case MachineCombinerPattern::Div2RecipEst:
+    switch (Root.getOpcode()) {
+    default:
guyblank wrote:
> currently in Haswell and newer cpus, the generated sequence is using fma instructions.
> this should be taken into account here in the patterns, right?
Yes this should be taken into account, but it does mean that the number of codegen patterns is going to start to balloon if we're not careful.


More information about the llvm-commits mailing list