[llvm] r294124 - [globalisel][arm] Tablegen-erate current Register Bank Information.
Daniel Sanders via llvm-commits
llvm-commits at lists.llvm.org
Sun Feb 5 04:07:55 PST 2017
Author: dsanders
Date: Sun Feb 5 06:07:55 2017
New Revision: 294124
URL: http://llvm.org/viewvc/llvm-project?rev=294124&view=rev
Log:
[globalisel][arm] Tablegen-erate current Register Bank Information.
Summary:
This patch tablegen-erates the ARM register bank information so that the
static tables added in D27807 no longer need to be maintained.
Depends on D27338
Reviewers: t.p.northover, rovka, ab, qcolombet, aditya_nandakumar
Reviewed By: rovka
Subscribers: aemerson, rengolin, mgorny, dberris, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D28567
Added:
llvm/trunk/lib/Target/ARM/ARMRegisterBanks.td
Modified:
llvm/trunk/lib/Target/ARM/ARM.td
llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp
llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.h
llvm/trunk/lib/Target/ARM/CMakeLists.txt
Modified: llvm/trunk/lib/Target/ARM/ARM.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.td?rev=294124&r1=294123&r2=294124&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARM.td (original)
+++ llvm/trunk/lib/Target/ARM/ARM.td Sun Feb 5 06:07:55 2017
@@ -848,6 +848,8 @@ def : ProcessorModel<"cortex-r52", Corte
include "ARMRegisterInfo.td"
+include "ARMRegisterBanks.td"
+
include "ARMCallingConv.td"
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp?rev=294124&r1=294123&r2=294124&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp Sun Feb 5 06:07:55 2017
@@ -18,6 +18,9 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/Target/TargetRegisterInfo.h"
+#define GET_TARGET_REGBANK_IMPL
+#include "ARMGenRegisterBank.inc"
+
using namespace llvm;
#ifndef LLVM_BUILD_GLOBAL_ISEL
@@ -29,37 +32,6 @@ using namespace llvm;
// into an ARMGenRegisterBankInfo.def (similar to AArch64).
namespace llvm {
namespace ARM {
-const uint32_t GPRCoverageData[] = {
- // Classes 0-31
- (1u << ARM::GPRRegClassID) | (1u << ARM::GPRwithAPSRRegClassID) |
- (1u << ARM::GPRnopcRegClassID) | (1u << ARM::rGPRRegClassID) |
- (1u << ARM::hGPRRegClassID) | (1u << ARM::tGPRRegClassID) |
- (1u << ARM::GPRnopc_and_hGPRRegClassID) |
- (1u << ARM::hGPR_and_rGPRRegClassID) | (1u << ARM::tcGPRRegClassID) |
- (1u << ARM::tGPR_and_tcGPRRegClassID) | (1u << ARM::GPRspRegClassID) |
- (1u << ARM::hGPR_and_tcGPRRegClassID),
- // Classes 32-63
- 0,
- // Classes 64-96
- 0,
- // FIXME: Some of the entries below this point can be safely removed once
- // this is tablegenerated. It's only needed because of the hardcoded
- // register class limit.
- // Classes 97-128
- 0,
- // Classes 129-160
- 0,
- // Classes 161-192
- 0,
- // Classes 193-224
- 0,
-};
-
-// FIXME: The 200 will be replaced by the number of register classes when this is
-// tablegenerated.
-RegisterBank GPRRegBank(ARM::GPRRegBankID, "GPRB", 32, ARM::GPRCoverageData, 200);
-RegisterBank *RegBanks[] = {&GPRRegBank};
-
RegisterBankInfo::PartialMapping GPRPartialMapping{0, 32, GPRRegBank};
RegisterBankInfo::ValueMapping ValueMappings[] = {
@@ -68,7 +40,7 @@ RegisterBankInfo::ValueMapping ValueMapp
} // end namespace llvm
ARMRegisterBankInfo::ARMRegisterBankInfo(const TargetRegisterInfo &TRI)
- : RegisterBankInfo(ARM::RegBanks, ARM::NumRegisterBanks) {
+ : ARMGenRegisterBankInfo() {
static bool AlreadyInit = false;
// We have only one set of register banks, whatever the subtarget
// is. Therefore, the initialization of the RegBanks table should be
Modified: llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.h?rev=294124&r1=294123&r2=294124&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.h Sun Feb 5 06:07:55 2017
@@ -16,19 +16,20 @@
#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
+#define GET_REGBANK_DECLARATIONS
+#include "ARMGenRegisterBank.inc"
+
namespace llvm {
class TargetRegisterInfo;
-namespace ARM {
-enum {
- GPRRegBankID = 0, // General purpose registers
- NumRegisterBanks,
+class ARMGenRegisterBankInfo : public RegisterBankInfo {
+#define GET_TARGET_REGBANK_CLASS
+#include "ARMGenRegisterBank.inc"
};
-} // end namespace ARM
/// This class provides the information for the target register banks.
-class ARMRegisterBankInfo final : public RegisterBankInfo {
+class ARMRegisterBankInfo final : public ARMGenRegisterBankInfo {
public:
ARMRegisterBankInfo(const TargetRegisterInfo &TRI);
Added: llvm/trunk/lib/Target/ARM/ARMRegisterBanks.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterBanks.td?rev=294124&view=auto
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMRegisterBanks.td (added)
+++ llvm/trunk/lib/Target/ARM/ARMRegisterBanks.td Sun Feb 5 06:07:55 2017
@@ -0,0 +1,13 @@
+//=- ARMRegisterBank.td - Describe the AArch64 Banks ---------*- tablegen -*-=//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+//
+//===----------------------------------------------------------------------===//
+
+def GPRRegBank : RegisterBank<"GPRB", [GPR, GPRwithAPSR]>;
Modified: llvm/trunk/lib/Target/ARM/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/CMakeLists.txt?rev=294124&r1=294123&r2=294124&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/ARM/CMakeLists.txt Sun Feb 5 06:07:55 2017
@@ -1,5 +1,6 @@
set(LLVM_TARGET_DEFINITIONS ARM.td)
+tablegen(LLVM ARMGenRegisterBank.inc -gen-register-bank)
tablegen(LLVM ARMGenRegisterInfo.inc -gen-register-info)
tablegen(LLVM ARMGenInstrInfo.inc -gen-instr-info)
tablegen(LLVM ARMGenMCCodeEmitter.inc -gen-emitter)
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