[llvm] r293894 - [Hexagon] Rename TypeCOMPOUND to TypeCJ
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 2 07:03:30 PST 2017
Author: kparzysz
Date: Thu Feb 2 09:03:30 2017
New Revision: 293894
URL: http://llvm.org/viewvc/llvm-project?rev=293894&view=rev
Log:
[Hexagon] Rename TypeCOMPOUND to TypeCJ
Modified:
llvm/trunk/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
llvm/trunk/lib/Target/Hexagon/HexagonInstrFormatsV4.td
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
Modified: llvm/trunk/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp?rev=293894&r1=293893&r2=293894&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp Thu Feb 2 09:03:30 2017
@@ -332,7 +332,7 @@ DecodeStatus HexagonDisassembler::getSin
// follow the duplex model, so the register values in the MCInst are
// incorrect. If the instruction is a compound, loop through the
// operands and change registers appropriately.
- if (HexagonMCInstrInfo::getType(*MCII, MI) == HexagonII::TypeCOMPOUND) {
+ if (HexagonMCInstrInfo::getType(*MCII, MI) == HexagonII::TypeCJ) {
for (MCInst::iterator i = MI.begin(), last = MI.end(); i < last; ++i) {
if (i->isReg()) {
unsigned reg = i->getReg() - Hexagon::R0;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrFormatsV4.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrFormatsV4.td?rev=293894&r1=293893&r2=293894&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrFormatsV4.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrFormatsV4.td Thu Feb 2 09:03:30 2017
@@ -17,10 +17,10 @@
// *** Must match BaseInfo.h ***
//----------------------------------------------------------------------------//
-def TypeV4LDST : IType<9>;
+def TypeV4LDST : IType<9>;
def TypeNV : IType<10>;
def TypeDUPLEX : IType<11>;
-def TypeCOMPOUND : IType<12>;
+def TypeCJ : IType<12>;
def TypePREFIX : IType<30>;
// Duplex Instruction Class Declaration
@@ -150,11 +150,11 @@ class SUBInst<dag outs, dag ins, string
class CJInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
string cstr = "">
- : InstHexagon<outs, ins, asmstr, pattern, cstr, COMPOUND_CJ_ARCHDEPSLOT, TypeCOMPOUND>,
+ : InstHexagon<outs, ins, asmstr, pattern, cstr, COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>,
OpcodeHexagon;
class CJInst_JMPSET<dag outs, dag ins, string asmstr, list<dag> pattern = [],
string cstr = "">
- : InstHexagon<outs, ins, asmstr, pattern, cstr, COMPOUND, TypeCOMPOUND>,
+ : InstHexagon<outs, ins, asmstr, pattern, cstr, COMPOUND, TypeCJ>,
OpcodeHexagon;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp?rev=293894&r1=293893&r2=293894&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp Thu Feb 2 09:03:30 2017
@@ -1713,7 +1713,7 @@ bool HexagonInstrInfo::isComplex(const M
// Return true if the instruction is a compund branch instruction.
bool HexagonInstrInfo::isCompoundBranchInstr(const MachineInstr &MI) const {
- return (getType(MI) == HexagonII::TypeCOMPOUND && MI.isBranch());
+ return getType(MI) == HexagonII::TypeCJ && MI.isBranch();
}
bool HexagonInstrInfo::isCondInst(const MachineInstr &MI) const {
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td?rev=293894&r1=293893&r2=293894&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td Thu Feb 2 09:03:30 2017
@@ -3056,7 +3056,7 @@ class CJInst_tstbit_R0<string px, bit np
: InstHexagon<(outs), (ins IntRegs:$Rs, brtarget:$r9_2),
""#px#" = tstbit($Rs, #0); if ("
#!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2",
- [], "", COMPOUND_CJ_ARCHDEPSLOT, TypeCOMPOUND>, OpcodeHexagon {
+ [], "", COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, OpcodeHexagon {
bits<4> Rs;
bits<11> r9_2;
@@ -3102,7 +3102,7 @@ class CJInst_RR<string px, string op, bi
: InstHexagon<(outs), (ins IntRegs:$Rs, IntRegs:$Rt, brtarget:$r9_2),
""#px#" = cmp."#op#"($Rs, $Rt); if ("
#!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2",
- [], "", COMPOUND_CJ_ARCHDEPSLOT, TypeCOMPOUND>, OpcodeHexagon {
+ [], "", COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, OpcodeHexagon {
bits<4> Rs;
bits<4> Rt;
bits<11> r9_2;
@@ -3156,7 +3156,7 @@ class CJInst_RU5<string px, string op, b
: InstHexagon<(outs), (ins IntRegs:$Rs, u5_0Imm:$U5, brtarget:$r9_2),
""#px#" = cmp."#op#"($Rs, #$U5); if ("
#!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2",
- [], "", COMPOUND_CJ_ARCHDEPSLOT, TypeCOMPOUND>, OpcodeHexagon {
+ [], "", COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, OpcodeHexagon {
bits<4> Rs;
bits<5> U5;
bits<11> r9_2;
@@ -3211,7 +3211,7 @@ class CJInst_Rn1<string px, string op, b
: InstHexagon<(outs), (ins IntRegs:$Rs, n1Const:$n1, brtarget:$r9_2),
""#px#" = cmp."#op#"($Rs,#$n1); if ("
#!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2",
- [], "", COMPOUND_CJ_ARCHDEPSLOT, TypeCOMPOUND>, OpcodeHexagon {
+ [], "", COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, OpcodeHexagon {
bits<4> Rs;
bits<11> r9_2;
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp?rev=293894&r1=293893&r2=293894&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp Thu Feb 2 09:03:30 2017
@@ -524,8 +524,7 @@ public:
bool Relaxable = false;
// Branches and loop-setup insns are handled as necessary by relaxation.
if (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeJ ||
- (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) ==
- HexagonII::TypeCOMPOUND &&
+ (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeCJ &&
MCID.isBranch()) ||
(llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeNV &&
MCID.isBranch()) ||
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h?rev=293894&r1=293893&r2=293894&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h (original)
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h Thu Feb 2 09:03:30 2017
@@ -44,7 +44,7 @@ namespace HexagonII {
TypeV4LDST = 9,
TypeNV = 10,
TypeDUPLEX = 11,
- TypeCOMPOUND = 12,
+ TypeCJ = 12,
TypeCVI_FIRST = 13,
TypeCVI_VA = TypeCVI_FIRST,
TypeCVI_VA_DV = 14,
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp?rev=293894&r1=293893&r2=293894&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp Thu Feb 2 09:03:30 2017
@@ -126,7 +126,7 @@ void HexagonMCCodeEmitter::EncodeSingleI
" `" << HexagonMCInstrInfo::getName(MCII, HMB) << "'"
"\n");
- if (llvm::HexagonMCInstrInfo::getType(MCII, HMB) == HexagonII::TypeCOMPOUND) {
+ if (llvm::HexagonMCInstrInfo::getType(MCII, HMB) == HexagonII::TypeCJ) {
for (unsigned i = 0; i < HMB.getNumOperands(); ++i)
if (HMB.getOperand(i).isReg()) {
unsigned Reg =
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp?rev=293894&r1=293893&r2=293894&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp Thu Feb 2 09:03:30 2017
@@ -438,7 +438,7 @@ bool HexagonMCInstrInfo::isCofMax1(MCIns
bool HexagonMCInstrInfo::isCompound(MCInstrInfo const &MCII,
MCInst const &MCI) {
- return (getType(MCII, MCI) == HexagonII::TypeCOMPOUND);
+ return getType(MCII, MCI) == HexagonII::TypeCJ;
}
bool HexagonMCInstrInfo::isDblRegForSubInst(unsigned Reg) {
@@ -470,7 +470,7 @@ bool HexagonMCInstrInfo::isConstExtended
return true;
// Branch insns are handled as necessary by relaxation.
if ((HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeJ) ||
- (HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCOMPOUND &&
+ (HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCJ &&
HexagonMCInstrInfo::getDesc(MCII, MCI).isBranch()) ||
(HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeNV &&
HexagonMCInstrInfo::getDesc(MCII, MCI).isBranch()))
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