[llvm] r293886 - [ARM] GlobalISel: Legalize loading pointers

[Diana Picus via llvm-commits]

Author: rovka
Date: Thu Feb  2 07:20:49 2017
New Revision: 293886

URL: http://llvm.org/viewvc/llvm-project?rev=293886&view=rev
Log:
[ARM] GlobalISel: Legalize loading pointers

Make it legal to load pointer values. Also check that pointers are assigned
to the GPR reg bank by default.

Modified:
    llvm/trunk/lib/Target/ARM/ARMLegalizerInfo.cpp
    llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
    llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir

Modified: llvm/trunk/lib/Target/ARM/ARMLegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLegalizerInfo.cpp?rev=293886&r1=293885&r2=293886&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMLegalizerInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMLegalizerInfo.cpp Thu Feb  2 07:20:49 2017
@@ -35,7 +35,7 @@ ARMLegalizerInfo::ARMLegalizerInfo() {
 
   setAction({G_FRAME_INDEX, p0}, Legal);
 
-  for (auto Ty : {s1, s8, s16, s32})
+  for (auto Ty : {s1, s8, s16, s32, p0})
     setAction({G_LOAD, Ty}, Legal);
   setAction({G_LOAD, 1, p0}, Legal);
 

Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir?rev=293886&r1=293885&r2=293886&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir Thu Feb  2 07:20:49 2017
@@ -8,6 +8,7 @@
   define void @test_add_s32() { ret void }
 
   define void @test_load_from_stack() { ret void }
+  define void @test_legal_loads() { ret void }
 ...
 ---
 name:            test_sext_s8
@@ -156,3 +157,36 @@ body:             |
     %1(s32) = G_LOAD %0(p0)
     BX_RET 14, _
 ...
+---
+name:            test_legal_loads
+# CHECK-LABEL: name: test_legal_loads
+legalized:       false
+# CHECK: legalized: true
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: _ }
+  - { id: 5, class: _ }
+body:             |
+  bb.0:
+    liveins: %r0, %r1, %r2, %r3
+
+    ; These are all legal, so we should find them unchanged in the output
+    ; CHECK-DAG: {{%[0-9]+}}(s32) = G_LOAD %0
+    ; CHECK-DAG: {{%[0-9]+}}(s16) = G_LOAD %0
+    ; CHECK-DAG: {{%[0-9]+}}(s8) = G_LOAD %0
+    ; CHECK-DAG: {{%[0-9]+}}(s1) = G_LOAD %0
+    ; CHECK-DAG: {{%[0-9]+}}(p0) = G_LOAD %0
+    %0(p0) = COPY %r0
+    %1(s32) = G_LOAD %0(p0)
+    %2(s16) = G_LOAD %0(p0)
+    %3(s8)  = G_LOAD %0(p0)
+    %4(s1)  = G_LOAD %0(p0)
+    %5(p0)  = G_LOAD %0(p0)
+    BX_RET 14, _
+...

Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir?rev=293886&r1=293885&r2=293886&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir Thu Feb  2 07:20:49 2017
@@ -123,6 +123,7 @@ selected:        false
 # CHECK: - { id: 2, class: gprb }
 # CHECK: - { id: 3, class: gprb }
 # CHECK: - { id: 4, class: gprb }
+# CHECK: - { id: 5, class: gprb }
 
 registers:
   - { id: 0, class: _ }
@@ -130,6 +131,7 @@ registers:
   - { id: 2, class: _ }
   - { id: 3, class: _ }
   - { id: 4, class: _ }
+  - { id: 5, class: _ }
 body:             |
   bb.0:
     liveins: %r0
@@ -138,6 +140,7 @@ body:             |
     %2(s16) = G_LOAD %0
     %3(s8)  = G_LOAD %0
     %4(s1)  = G_LOAD %0
+    %5(p0)  = G_LOAD %0
     BX_RET 14, _, implicit %r0
 
 ...