[PATCH] D29289: [PowerPC] pseudo instruction EH_SjLj_LongJmp64 requires G8RC_NOX0 register

[Kit Barton via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL293769: [PowerPC] Fix sjlj pseduo instructions to use G8RC_NOX0 register class (authored by kbarton).

Changed prior to commit:
  https://reviews.llvm.org/D29289?vs=86303&id=86626#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D29289

Files:
  llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/trunk/test/CodeGen/PowerPC/sjlj_no0x.ll


Index: llvm/trunk/test/CodeGen/PowerPC/sjlj_no0x.ll
===================================================================
--- llvm/trunk/test/CodeGen/PowerPC/sjlj_no0x.ll
+++ llvm/trunk/test/CodeGen/PowerPC/sjlj_no0x.ll
@@ -0,0 +1,29 @@
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -verify-machineinstrs | FileCheck %s
+
+target datalayout = "e-m:e-i64:64-n32:64"
+target triple = "powerpc64le-unknown-linux-gnu"
+
+; Function Attrs: noinline nounwind
+define void @_Z23BuiltinLongJmpFunc1_bufv() #0 {
+entry:
+  call void @llvm.eh.sjlj.longjmp(i8* bitcast (void ()* @_Z23BuiltinLongJmpFunc1_bufv to i8*))
+  unreachable
+
+; CHECK: @_Z23BuiltinLongJmpFunc1_bufv
+; CHECK: addis [[REG:[0-9]+]], 2, .LC0 at toc@ha
+; CHECK: ld 31, 0([[REG]])
+; CHECK: ld [[REG2:[0-9]+]], 8([[REG]])
+; CHECK-DAG: ld 1, 16([[REG]])
+; CHECK-DAG: ld 30, 32([[REG]])
+; CHECK-DAG: ld 2, 24([[REG]])
+; CHECK-DAG: mtctr [[REG2]]
+; CHECK: bctr
+
+return:                                           ; No predecessors!
+  ret void
+}
+
+; Function Attrs: noreturn nounwind
+declare void @llvm.eh.sjlj.longjmp(i8*) #1
Index: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
===================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
@@ -770,9 +770,10 @@
 }
 
 // A single-register address. This is used with the SjLj
-// pseudo-instructions.
+// pseudo-instructions which tranlates to LD/LWZ.  These instructions requires
+// G8RC_NOX0 registers.
 def memr : Operand<iPTR> {
-  let MIOperandInfo = (ops ptr_rc:$ptrreg);
+  let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg);
 }
 def PPCTLSRegOperand : AsmOperandClass {
   let Name = "TLSReg"; let PredicateMethod = "isTLSReg";


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