[PATCH] D29127: [ARM] Classification Improvements to ARM Sched-Model. NFCI.
Diana Picus via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 1 02:12:28 PST 2017
rovka added a comment.
I'm not sure if it's you or Phab, but I'm only seeing the changes between the first patch and the current one (not between trunk and the current one). You might want to try to upload again with all the changes included.
Comment at: test/CodeGen/ARM/misched-int-basic.ll:1
; REQUIRES: asserts
; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-a9 -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > \
Nitpick: Why this is an IR test and not an MIR test?
Comment at: test/CodeGen/ARM/misched-int-basic.ll:49
+ %convc = sext i16 %tmp to i32
+ %mul0 = mul nsw i32 %convc, %convc
+ %mul = mul nsw i32 %add, %mul0
This looks a bit contrived, is there any reason why you don't use mul i16 %c, %c to get a smulbb?
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