[PATCH] D29325: AMDGPU/SI: Attempt to fix inst-select-load-smrd.mir on some builds

[Phabricator via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL293639: AMDGPU/SI: Fix inst-select-load-smrd.mir on some builds (authored by tstellar).

Changed prior to commit:
  https://reviews.llvm.org/D29325?vs=86417&id=86433#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D29325

Files:
  llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
  llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-smrd.mir


Index: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-smrd.mir
===================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-smrd.mir
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-smrd.mir
@@ -52,11 +52,11 @@
 # SIVI: [[K_LO:%[0-9]+]] = S_MOV_B32 4294967292
 # SIVI: [[K_HI:%[0-9]+]] = S_MOV_B32 3
 # SIVI: [[K:%[0-9]+]] = REG_SEQUENCE [[K_LO]], 1, [[K_HI]], 2
-# SIVI: [[K_SUB0:%[0-9]+]] = COPY [[K]].sub0
-# SIVI: [[PTR_LO:%[0-9]+]] = COPY [[PTR]].sub0
+# SIVI-DAG: [[K_SUB0:%[0-9]+]] = COPY [[K]].sub0
+# SIVI-DAG: [[PTR_LO:%[0-9]+]] = COPY [[PTR]].sub0
 # SIVI: [[ADD_PTR_LO:%[0-9]+]] = S_ADD_U32 [[PTR_LO]], [[K_SUB0]]
-# SIVI: [[K_SUB1:%[0-9]+]] = COPY [[K]].sub1
-# SIVI: [[PTR_HI:%[0-9]+]] = COPY [[PTR]].sub1
+# SIVI-DAG: [[K_SUB1:%[0-9]+]] = COPY [[K]].sub1
+# SIVI-DAG: [[PTR_HI:%[0-9]+]] = COPY [[PTR]].sub1
 # SIVI: [[ADD_PTR_HI:%[0-9]+]] = S_ADDC_U32 [[PTR_HI]], [[K_SUB1]]
 # SIVI: [[ADD_PTR:%[0-9]+]] = REG_SEQUENCE [[ADD_PTR_LO]], 1, [[ADD_PTR_HI]], 2
 # SIVI: S_LOAD_DWORD_IMM [[ADD_PTR]], 0, 0
@@ -66,11 +66,11 @@
 # GCN: [[K_LO:%[0-9]+]] = S_MOV_B32 0
 # GCN: [[K_HI:%[0-9]+]] = S_MOV_B32 4
 # GCN: [[K:%[0-9]+]] = REG_SEQUENCE [[K_LO]], 1, [[K_HI]], 2
-# GCN: [[K_SUB0:%[0-9]+]] = COPY [[K]].sub0
-# GCN: [[PTR_LO:%[0-9]+]] = COPY [[PTR]].sub0
+# GCN-DAG: [[K_SUB0:%[0-9]+]] = COPY [[K]].sub0
+# GCN-DAG: [[PTR_LO:%[0-9]+]] = COPY [[PTR]].sub0
 # GCN: [[ADD_PTR_LO:%[0-9]+]] = S_ADD_U32 [[PTR_LO]], [[K_SUB0]]
-# GCN: [[K_SUB1:%[0-9]+]] = COPY [[K]].sub1
-# GCN: [[PTR_HI:%[0-9]+]] = COPY [[PTR]].sub1
+# GCN-DAG: [[K_SUB1:%[0-9]+]] = COPY [[K]].sub1
+# GCN-DAG: [[PTR_HI:%[0-9]+]] = COPY [[PTR]].sub1
 # GCN: [[ADD_PTR_HI:%[0-9]+]] = S_ADDC_U32 [[PTR_HI]], [[K_SUB1]]
 # GCN: [[ADD_PTR:%[0-9]+]] = REG_SEQUENCE [[ADD_PTR_LO]], 1, [[ADD_PTR_HI]], 2
 # GCN: S_LOAD_DWORD_IMM [[ADD_PTR]], 0, 0
@@ -87,11 +87,11 @@
 # SIVI: [[K_LO:%[0-9]+]] = S_MOV_B32 0
 # SIVI: [[K_HI:%[0-9]+]] = S_MOV_B32 1
 # SIVI: [[K:%[0-9]+]] = REG_SEQUENCE [[K_LO]], 1, [[K_HI]], 2
-# SIVI: [[K_SUB0:%[0-9]+]] = COPY [[K]].sub0
-# SIVI: [[PTR_LO:%[0-9]+]] = COPY [[PTR]].sub0
+# SIVI-DAG: [[K_SUB0:%[0-9]+]] = COPY [[K]].sub0
+# SIVI-DAG: [[PTR_LO:%[0-9]+]] = COPY [[PTR]].sub0
 # SIVI: [[ADD_PTR_LO:%[0-9]+]] = S_ADD_U32 [[PTR_LO]], [[K_SUB0]]
-# SIVI: [[K_SUB1:%[0-9]+]] = COPY [[K]].sub1
-# SIVI: [[PTR_HI:%[0-9]+]] = COPY [[PTR]].sub1
+# SIVI-DAG: [[K_SUB1:%[0-9]+]] = COPY [[K]].sub1
+# SIVI-DAG: [[PTR_HI:%[0-9]+]] = COPY [[PTR]].sub1
 # SIVI: [[ADD_PTR_HI:%[0-9]+]] = S_ADDC_U32 [[PTR_HI]], [[K_SUB1]]
 # SIVI: [[ADD_PTR:%[0-9]+]] = REG_SEQUENCE [[ADD_PTR_LO]], 1, [[ADD_PTR_HI]], 2
 # SIVI: S_LOAD_DWORD_IMM [[ADD_PTR]], 0, 0
Index: llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -84,13 +84,19 @@
 
   DebugLoc DL = I.getDebugLoc();
 
+  MachineOperand Lo1(getSubOperand64(I.getOperand(1), AMDGPU::sub0));
+  MachineOperand Lo2(getSubOperand64(I.getOperand(2), AMDGPU::sub0));
+
   BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_ADD_U32), DstLo)
-          .add(getSubOperand64(I.getOperand(1), AMDGPU::sub0))
-          .add(getSubOperand64(I.getOperand(2), AMDGPU::sub0));
+          .add(Lo1)
+          .add(Lo2);
+
+  MachineOperand Hi1(getSubOperand64(I.getOperand(1), AMDGPU::sub1));
+  MachineOperand Hi2(getSubOperand64(I.getOperand(2), AMDGPU::sub1));
 
   BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_ADDC_U32), DstHi)
-          .add(getSubOperand64(I.getOperand(1), AMDGPU::sub1))
-          .add(getSubOperand64(I.getOperand(2), AMDGPU::sub1));
+          .add(Hi1)
+          .add(Hi2);
 
   BuildMI(*BB, &I, DL, TII.get(AMDGPU::REG_SEQUENCE), I.getOperand(0).getReg())
           .addReg(DstLo)


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