[llvm] r293561 - [X86][SSE] Fix unsigned <= 0 warning in assert. NFCI.

Simon Pilgrim via llvm-commits llvm-commits at lists.llvm.org
Mon Jan 30 14:58:45 PST 2017


Author: rksimon
Date: Mon Jan 30 16:58:44 2017
New Revision: 293561

URL: http://llvm.org/viewvc/llvm-project?rev=293561&view=rev
Log:
[X86][SSE] Fix unsigned <= 0 warning in assert. NFCI.

Thanks to @mkuper

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=293561&r1=293560&r2=293561&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Jan 30 16:58:44 2017
@@ -5775,14 +5775,14 @@ static bool getFauxShuffleMask(SDValue N
     SDValue InVec = N.getOperand(0);
     SDValue InScl = N.getOperand(1);
     uint64_t InIdx = N.getConstantOperandVal(2);
-    assert(0 <= InIdx && InIdx < NumElts && "Illegal insertion index");
+    assert(InIdx < NumElts && "Illegal insertion index");
     if (InScl.getOpcode() != ISD::AssertZext ||
         InScl.getOperand(0).getOpcode() != X86ISD::PEXTRW)
       return false;
 
     SDValue ExVec = InScl.getOperand(0).getOperand(0);
     uint64_t ExIdx = InScl.getOperand(0).getConstantOperandVal(1);
-    assert(0 <= ExIdx && ExIdx < NumElts && "Illegal extraction index");
+    assert(ExIdx < NumElts && "Illegal extraction index");
     Ops.push_back(InVec);
     Ops.push_back(ExVec);
     for (unsigned i = 0; i != NumElts; ++i)




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