[PATCH] D10533: [AArch64][ARM] Match interleaved memory accesses into ldN/stN/vldN/vstN intrinsics.

Renato Golin via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Jan 30 14:59:25 PST 2017

rengolin added a comment.

In https://reviews.llvm.org/D10533#660846, @MatzeB wrote:

> Is there a reason this was implemented as an IR pass and not at the SelectionDAG level?

Wow, this brings back memories, but unfortunately not the reason for an additional pass. I think it was something to do with being after the register allocation, though I may be misquoting someone.



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