[PATCH] D29177: [PowerPC][Altivec] Add mfvrd extended mnemonic

[Bruno Rosa via Phabricator via llvm-commits]

brunoalr created this revision.

mfvrd is an alias to mfvrsd.
This patch enables correct parsing of the alias, but we still emit a mfvrsd.

Patch by nemanjai


Repository:
  rL LLVM

https://reviews.llvm.org/D29177

Files:
  PPCInstrVSX.td


Index: PPCInstrVSX.td
===================================================================
--- PPCInstrVSX.td
+++ PPCInstrVSX.td
@@ -1410,6 +1410,11 @@
                               "mfvsrd $rA, $XT", IIC_VecGeneral,
                               [(set i64:$rA, (PPCmfvsr f64:$XT))]>,
       Requires<[In64BitMode]>;
+  let isCodeGenOnly = 1 in
+  def MFVRD : XX1_RS6_RD5_XO<31, 51, (outs g8rc:$rA), (ins vrrc:$XT),
+                             "mfvsrd $rA, $XT", IIC_VecGeneral,
+                             []>,
+      Requires<[In64BitMode]>;
   def MFVSRWZ : XX1_RS6_RD5_XO<31, 115, (outs gprc:$rA), (ins vsfrc:$XT),
                                "mfvsrwz $rA, $XT", IIC_VecGeneral,
                                [(set i32:$rA, (PPCmfvsr f64:$XT))]>;
@@ -1440,6 +1445,11 @@
 } // IsISA3_0, HasDirectMove
 } // UseVSXReg = 1
 
+// We want to parse this from asm, but we don't want to emit this as it would
+// be emitted with a VSX reg. So leave Emit = 0 here.
+def : InstAlias<"mfvrd $rA, $XT",
+                (MFVRD g8rc:$rA, vrrc:$XT), 0>;
+
 /*  Direct moves of various widths from GPR's into VSR's. Each move lines
     the value up into element 0 (both BE and LE). Namely, entities smaller than
     a doubleword are shifted left and moved for BE. For LE, they're moved, then


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D29177.85896.patch
Type: text/x-patch
Size: 1294 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20170126/bc460888/attachment.bin>