[llvm] r293081 - AMDGPU: Set call_convention bit in kernel_code_t

[Matt Arsenault via llvm-commits]

Author: arsenm
Date: Wed Jan 25 14:21:57 2017
New Revision: 293081

URL: http://llvm.org/viewvc/llvm-project?rev=293081&view=rev
Log:
AMDGPU: Set call_convention bit in kernel_code_t

According to the documentation this is supposed to be -1
if indirect calls are not supported.

Modified:
    llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
    llvm/trunk/test/CodeGen/AMDGPU/hsa.ll
    llvm/trunk/test/MC/AMDGPU/hsa-exp.s
    llvm/trunk/test/MC/AMDGPU/hsa.s

Modified: llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp?rev=293081&r1=293080&r2=293081&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp Wed Jan 25 14:21:57 2017
@@ -127,6 +127,11 @@ void initDefaultAMDKernelCodeT(amd_kerne
   Header.kernel_code_entry_byte_offset = sizeof(Header);
   // wavefront_size is specified as a power of 2: 2^6 = 64 threads.
   Header.wavefront_size = 6;
+
+  // If the code object does not support indirect functions, then the value must
+  // be 0xffffffff.
+  Header.call_convention = -1;
+
   // These alignment values are specified in powers of two, so alignment =
   // 2^n.  The minimum alignment is 2^4 = 16.
   Header.kernarg_segment_alignment = 4;

Modified: llvm/trunk/test/CodeGen/AMDGPU/hsa.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/hsa.ll?rev=293081&r1=293080&r2=293081&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/hsa.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/hsa.ll Wed Jan 25 14:21:57 2017
@@ -45,6 +45,8 @@
 ; HSA: .amd_kernel_code_t
 ; HSA: enable_sgpr_private_segment_buffer = 1
 ; HSA: enable_sgpr_kernarg_segment_ptr = 1
+; HSA: wavefront_size = 6
+; HSA: call_convention = -1
 ; HSA: .end_amd_kernel_code_t
 ; HSA: s_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x0
 

Modified: llvm/trunk/test/MC/AMDGPU/hsa-exp.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/hsa-exp.s?rev=293081&r1=293080&r2=293081&view=diff
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/hsa-exp.s (original)
+++ llvm/trunk/test/MC/AMDGPU/hsa-exp.s Wed Jan 25 14:21:57 2017
@@ -124,6 +124,6 @@ amd_kernel_code_t_minimal:
 // ASM:	group_segment_alignment = 4
 // ASM:	private_segment_alignment = 4
 // ASM:	wavefront_size = 6
-// ASM:	call_convention = 0
+// ASM:	call_convention = -1
 // ASM:	runtime_loader_kernel_symbol = 0
 // ASM: .end_amd_kernel_code_t

Modified: llvm/trunk/test/MC/AMDGPU/hsa.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/hsa.s?rev=293081&r1=293080&r2=293081&view=diff
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/hsa.s (original)
+++ llvm/trunk/test/MC/AMDGPU/hsa.s Wed Jan 25 14:21:57 2017
@@ -273,6 +273,6 @@ amd_kernel_code_t_minimal:
 // ASM:	group_segment_alignment = 4
 // ASM:	private_segment_alignment = 4
 // ASM:	wavefront_size = 6
-// ASM:	call_convention = 0
+// ASM:	call_convention = -1
 // ASM:	runtime_loader_kernel_symbol = 0
 // ASM: .end_amd_kernel_code_t