ISD::ZERO_EXTEND / SIGN_EXTEND of sub-vectors

[Friedman, Eli via llvm-commits]

On 1/23/2017 11:47 PM, Jonas Paulsson wrote:
>>
> Thanks Eli - that seemed to do the trick! :-)
>
> I just added a few lines to convert the node to SIGN/ZERO 
> _EXTEND_VECTOR_INREG - see attachment.
>
> I am thinking that the WidenVT should be legal, and since it seems 
> GetWidenedVector() is supposed to always return a legal vector, I have 
> neither added a check for legality of InOp. All regression tests pass. 

Better to use "DAG.getSignExtendVectorInReg(..." rather than 
"DAG.getNode(ISD::SIGN_EXTEND_VECTOR_INREG, ...", probably.  (You might 
also be hiding some problems; it looks like the assertions which verify 
the input and output types are in getSignExtendVectorInReg rather than 
getNode.)

Are you sure "InOp" is the right input to the operation? 
SIGN_EXTEND_VECTOR_INREG expects that the input and the output are the 
same size, but you aren't doing anything to ensure that.

-Eli

-- 
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project

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