ISD::ZERO_EXTEND / SIGN_EXTEND of sub-vectors

[Simon Pilgrim via llvm-commits]

Out of interest, have you looked at the ISD::ZERO/SIGN_EXTEND_VECTOR_IN_REG ops instead?

We’re using them on x86/sse for vector extensions through to lowering and I’m currently investigating using them all the way to instruction selection (PR31712).

Simon.

> On 23 Jan 2017, at 14:52, Jonas Paulsson via llvm-commits <llvm-commits at lists.llvm.org> wrote:
> 
> Hi,
> 
> I am trying to fix these operations for the SystemZ backend. The problem is that if the vectors are only of "partial" length, for example just v2i32 which is just half of the vector register capacity, they get scalarized.
> 
> I tracked this down to WidenVecRes_Convert(), which does not manage to handle this. It seems it computes the number of elements of the legal type, which would be 4 as in v4i32, but this results in the illegal type of v4i16 which stops the transformation of the node and scalarization results.
> 
> I have made a patch for this that works for just the SystemZ backend, by implementing the ReplaceNodeResults() method in TargetLowering. See attached patch.
> 
> My question now is if this is of interest also to other targets, so that this should become part of the WidenVecRes_Convert()?
> 
> I am also curious if there is any simpler way of doing this? I tried
> 
> ---    if (InVTNumElts == WidenNumElts) {
> 
> +++    if (InVTNumElts >= WidenNumElts) {
> 
> , in WidenVec_Convert(), because it would make sense to allow for more input vector elements, since the would be outside of and undefined in the resulting vector. This however immediately triggered an assert for the SIGN_EXTEND node that did not have equal number of vector elements.
> 
> /Jonas
> 
> 
> 
> 
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