[PATCH] D29049: TableGen: Fix infinite recursion in RegisterBankEmitter

[Tom Stellard via Phabricator via llvm-commits]

tstellarAMD created this revision.
Herald added a subscriber: wdng.

AMDGPU has two register classes with the same set of registers, and this
was causing this tablegen backend would get stuck in infinite recursion.


https://reviews.llvm.org/D29049

Files:
  test/TableGen/RegisterBankEmitter.td
  utils/TableGen/RegisterBankEmitter.cpp


Index: utils/TableGen/RegisterBankEmitter.cpp
===================================================================
--- utils/TableGen/RegisterBankEmitter.cpp
+++ utils/TableGen/RegisterBankEmitter.cpp
@@ -177,7 +177,11 @@
         (Twine(Kind) + " (" + PossibleSubclass.getName() + ")").str();
 
     // Visit each subclass of an explicitly named class.
-    if (RC != &PossibleSubclass && RC->hasSubClass(&PossibleSubclass))
+    // If RC and PossibleSubclass are both sub-classes of each other, then
+    // we should skip the call to visitRegisterBankClasses() to avoid
+    // infinite recursion.
+    if (RC != &PossibleSubclass && RC->hasSubClass(&PossibleSubclass) &&
+        !PossibleSubclass.hasSubClass(RC))
       visitRegisterBankClasses(RegisterClassHierarchy, &PossibleSubclass,
                                TmpKind + " " + RC->getName() + " subclass",
                                VisitFn);
Index: test/TableGen/RegisterBankEmitter.td
===================================================================
--- /dev/null
+++ test/TableGen/RegisterBankEmitter.td
@@ -0,0 +1,12 @@
+// RUN: llvm-tblgen -gen-register-bank -I %p/../../include %s | FileCheck %s
+
+include "llvm/Target/Target.td"
+
+def MyTarget : Target;
+def R0 : Register<"r0">;
+let Size = 32 in {
+  def ClassA : RegisterClass<"MyTarget", [i32], 32, (add R0)>;
+  def ClassB : RegisterClass<"MyTarget", [i1], 32, (add ClassA)>;
+}
+// CHECK: MyTarget::GPRRegBank
+def GPRRegBank : RegisterBank<"GPR", [ClassA]>;


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