[llvm] r292587 - [ARM] Use helpers for adding pred / CC operands. NFC
Diana Picus via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 20 00:15:25 PST 2017
Author: rovka
Date: Fri Jan 20 02:15:24 2017
New Revision: 292587
URL: http://llvm.org/viewvc/llvm-project?rev=292587&view=rev
Log:
[ARM] Use helpers for adding pred / CC operands. NFC
Hunt down some of the places where we use bare addReg(0) or addImm(AL).addReg(0)
and replace with add(condCodeOp()) and add(predOps()). This should make it
easier to understand what those operands represent (without having to look at
the definition of the instruction that we're adding to).
Differential Revision: https://reviews.llvm.org/D27984
Modified:
llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp
llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp
llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp
llvm/trunk/lib/Target/ARM/ThumbRegisterInfo.cpp
Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=292587&r1=292586&r2=292587&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Fri Jan 20 02:15:24 2017
@@ -168,9 +168,8 @@ MachineInstr *ARMBaseInstrInfo::convertT
get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
.addReg(BaseReg)
.addImm(Amt)
- .addImm(Pred)
- .addReg(0)
- .addReg(0);
+ .add(predOps(Pred))
+ .add(condCodeOp());
} else if (Amt != 0) {
ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
@@ -180,17 +179,15 @@ MachineInstr *ARMBaseInstrInfo::convertT
.addReg(OffReg)
.addReg(0)
.addImm(SOOpc)
- .addImm(Pred)
- .addReg(0)
- .addReg(0);
+ .add(predOps(Pred))
+ .add(condCodeOp());
} else
UpdateMI = BuildMI(MF, MI.getDebugLoc(),
get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
.addReg(BaseReg)
.addReg(OffReg)
- .addImm(Pred)
- .addReg(0)
- .addReg(0);
+ .add(predOps(Pred))
+ .add(condCodeOp());
break;
}
case ARMII::AddrMode3 : {
@@ -202,17 +199,15 @@ MachineInstr *ARMBaseInstrInfo::convertT
get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
.addReg(BaseReg)
.addImm(Amt)
- .addImm(Pred)
- .addReg(0)
- .addReg(0);
+ .add(predOps(Pred))
+ .add(condCodeOp());
else
UpdateMI = BuildMI(MF, MI.getDebugLoc(),
get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
.addReg(BaseReg)
.addReg(OffReg)
- .addImm(Pred)
- .addReg(0)
- .addReg(0);
+ .add(predOps(Pred))
+ .add(condCodeOp());
break;
}
}
@@ -433,7 +428,7 @@ unsigned ARMBaseInstrInfo::insertBranch(
if (!FBB) {
if (Cond.empty()) { // Unconditional branch?
if (isThumb)
- BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).addImm(ARMCC::AL).addReg(0);
+ BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).add(predOps(ARMCC::AL));
else
BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
} else
@@ -450,7 +445,7 @@ unsigned ARMBaseInstrInfo::insertBranch(
.addImm(Cond[0].getImm())
.add(Cond[1]);
if (isThumb)
- BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).addImm(ARMCC::AL).addReg(0);
+ BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).add(predOps(ARMCC::AL));
else
BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
return 2;
@@ -2047,9 +2042,10 @@ void llvm::emitARMRegPlusImmediate(Machi
unsigned MIFlags) {
if (NumBytes == 0 && DestReg != BaseReg) {
BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), DestReg)
- .addReg(BaseReg, RegState::Kill)
- .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
- .setMIFlags(MIFlags);
+ .addReg(BaseReg, RegState::Kill)
+ .add(predOps(Pred, PredReg))
+ .add(condCodeOp())
+ .setMIFlags(MIFlags);
return;
}
@@ -2069,9 +2065,11 @@ void llvm::emitARMRegPlusImmediate(Machi
// Build the new ADD / SUB.
unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
- .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
- .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
- .setMIFlags(MIFlags);
+ .addReg(BaseReg, RegState::Kill)
+ .addImm(ThisVal)
+ .add(predOps(Pred, PredReg))
+ .add(condCodeOp())
+ .setMIFlags(MIFlags);
BaseReg = DestReg;
}
}
Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=292587&r1=292586&r2=292587&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Fri Jan 20 02:15:24 2017
@@ -425,10 +425,11 @@ void ARMBaseRegisterInfo::emitLoadConstP
unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
- .addReg(DestReg, getDefRegState(true), SubIdx)
- .addConstantPoolIndex(Idx)
- .addImm(0).addImm(Pred).addReg(PredReg)
- .setMIFlags(MIFlags);
+ .addReg(DestReg, getDefRegState(true), SubIdx)
+ .addConstantPoolIndex(Idx)
+ .addImm(0)
+ .add(predOps(Pred, PredReg))
+ .setMIFlags(MIFlags);
}
bool ARMBaseRegisterInfo::
Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp?rev=292587&r1=292586&r2=292587&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Fri Jan 20 02:15:24 2017
@@ -897,8 +897,9 @@ MachineBasicBlock *ARMConstantIslands::s
if (!isThumb)
BuildMI(OrigBB, DebugLoc(), TII->get(Opc)).addMBB(NewBB);
else
- BuildMI(OrigBB, DebugLoc(), TII->get(Opc)).addMBB(NewBB)
- .addImm(ARMCC::AL).addReg(0);
+ BuildMI(OrigBB, DebugLoc(), TII->get(Opc))
+ .addMBB(NewBB)
+ .add(predOps(ARMCC::AL));
++NumSplit;
// Update the CFG. All succs of OrigBB are now succs of NewBB.
@@ -1296,8 +1297,9 @@ void ARMConstantIslands::createNewWater(
if (!isThumb)
BuildMI(UserMBB, DebugLoc(), TII->get(UncondBr)).addMBB(NewMBB);
else
- BuildMI(UserMBB, DebugLoc(), TII->get(UncondBr)).addMBB(NewMBB)
- .addImm(ARMCC::AL).addReg(0);
+ BuildMI(UserMBB, DebugLoc(), TII->get(UncondBr))
+ .addMBB(NewMBB)
+ .add(predOps(ARMCC::AL));
unsigned MaxDisp = getUnconditionalBrDisp(UncondBr);
ImmBranches.push_back(ImmBranch(&UserMBB->back(),
MaxDisp, false, UncondBr));
@@ -1683,8 +1685,9 @@ ARMConstantIslands::fixupConditionalBr(I
Br.MI = &MBB->back();
BBInfo[MBB->getNumber()].Size += TII->getInstSizeInBytes(MBB->back());
if (isThumb)
- BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB)
- .addImm(ARMCC::AL).addReg(0);
+ BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr))
+ .addMBB(DestBB)
+ .add(predOps(ARMCC::AL));
else
BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB);
BBInfo[MBB->getNumber()].Size += TII->getInstSizeInBytes(MBB->back());
@@ -2240,13 +2243,11 @@ adjustJTTargetBlockForward(MachineBasicB
if (isThumb2)
BuildMI(NewBB, DebugLoc(), TII->get(ARM::t2B))
.addMBB(BB)
- .addImm(ARMCC::AL)
- .addReg(0);
+ .add(predOps(ARMCC::AL));
else
BuildMI(NewBB, DebugLoc(), TII->get(ARM::tB))
.addMBB(BB)
- .addImm(ARMCC::AL)
- .addReg(0);
+ .add(predOps(ARMCC::AL));
// Update internal data structures to account for the newly inserted MBB.
MF->RenumberBlocks(NewBB);
Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp?rev=292587&r1=292586&r2=292587&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Fri Jan 20 02:15:24 2017
@@ -696,8 +696,8 @@ void ARMExpandPseudo::ExpandMOV32BitImm(
HI16 = HI16.addImm(SOImmValV2);
LO16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
HI16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
- LO16.addImm(Pred).addReg(PredReg).addReg(0);
- HI16.addImm(Pred).addReg(PredReg).addReg(0);
+ LO16.addImm(Pred).addReg(PredReg).add(condCodeOp());
+ HI16.addImm(Pred).addReg(PredReg).add(condCodeOp());
TransferImpOps(MI, LO16, HI16);
MI.eraseFromParent();
return;
@@ -1028,7 +1028,7 @@ bool ARMExpandPseudo::ExpandMI(MachineBa
// Add the default predicate in Thumb mode.
if (STI->isThumb())
- MIB.addImm(ARMCC::AL).addReg(0);
+ MIB.add(predOps(ARMCC::AL));
} else if (RetOpcode == ARM::TCRETURNri) {
BuildMI(MBB, MBBI, dl,
TII.get(STI->isThumb() ? ARM::tTAILJMPr : ARM::TAILJMPr))
@@ -1064,7 +1064,7 @@ bool ARMExpandPseudo::ExpandMI(MachineBa
.add(MI.getOperand(2))
.addImm(MI.getOperand(3).getImm()) // 'pred'
.add(MI.getOperand(4))
- .addReg(0); // 's' bit
+ .add(condCodeOp()); // 's' bit
MI.eraseFromParent();
return true;
@@ -1076,7 +1076,7 @@ bool ARMExpandPseudo::ExpandMI(MachineBa
.addImm(MI.getOperand(3).getImm())
.addImm(MI.getOperand(4).getImm()) // 'pred'
.add(MI.getOperand(5))
- .addReg(0); // 's' bit
+ .add(condCodeOp()); // 's' bit
MI.eraseFromParent();
return true;
@@ -1089,7 +1089,7 @@ bool ARMExpandPseudo::ExpandMI(MachineBa
.addImm(MI.getOperand(4).getImm())
.addImm(MI.getOperand(5).getImm()) // 'pred'
.add(MI.getOperand(6))
- .addReg(0); // 's' bit
+ .add(condCodeOp()); // 's' bit
MI.eraseFromParent();
return true;
@@ -1113,7 +1113,7 @@ bool ARMExpandPseudo::ExpandMI(MachineBa
.addImm(MI.getOperand(2).getImm())
.addImm(MI.getOperand(3).getImm()) // 'pred'
.add(MI.getOperand(4))
- .addReg(0); // 's' bit
+ .add(condCodeOp()); // 's' bit
MI.eraseFromParent();
return true;
@@ -1126,7 +1126,7 @@ bool ARMExpandPseudo::ExpandMI(MachineBa
.addImm(MI.getOperand(2).getImm())
.addImm(MI.getOperand(3).getImm()) // 'pred'
.add(MI.getOperand(4))
- .addReg(0); // 's' bit
+ .add(condCodeOp()); // 's' bit
MI.eraseFromParent();
return true;
@@ -1149,7 +1149,7 @@ bool ARMExpandPseudo::ExpandMI(MachineBa
.addImm(MI.getOperand(3).getImm())
.addImm(MI.getOperand(4).getImm()) // 'pred'
.add(MI.getOperand(5))
- .addReg(0); // 's' bit
+ .add(condCodeOp()); // 's' bit
MI.eraseFromParent();
return true;
}
@@ -1222,7 +1222,7 @@ bool ARMExpandPseudo::ExpandMI(MachineBa
.add(MI.getOperand(1))
.addImm(ARM_AM::getSORegOpc(ARM_AM::rrx, 0))
.add(predOps(ARMCC::AL))
- .addReg(0);
+ .add(condCodeOp());
TransferImpOps(MI, MIB, MIB);
MI.eraseFromParent();
return true;
@@ -1231,10 +1231,9 @@ bool ARMExpandPseudo::ExpandMI(MachineBa
case ARM::TPsoft: {
MachineInstrBuilder MIB;
if (Opcode == ARM::tTPsoft)
- MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
- TII->get( ARM::tBL))
- .addImm((unsigned)ARMCC::AL).addReg(0)
- .addExternalSymbol("__aeabi_read_tp", 0);
+ MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tBL))
+ .add(predOps(ARMCC::AL))
+ .addExternalSymbol("__aeabi_read_tp", 0);
else
MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
TII->get( ARM::BL))
Modified: llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp?rev=292587&r1=292586&r2=292587&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp Fri Jan 20 02:15:24 2017
@@ -468,10 +468,10 @@ void ARMFrameLowering::emitPrologue(Mach
case CodeModel::Default:
case CodeModel::Kernel:
BuildMI(MBB, MBBI, dl, TII.get(ARM::tBL))
- .addImm((unsigned)ARMCC::AL).addReg(0)
- .addExternalSymbol("__chkstk")
- .addReg(ARM::R4, RegState::Implicit)
- .setMIFlags(MachineInstr::FrameSetup);
+ .add(predOps(ARMCC::AL))
+ .addExternalSymbol("__chkstk")
+ .addReg(ARM::R4, RegState::Implicit)
+ .setMIFlags(MachineInstr::FrameSetup);
break;
case CodeModel::Large:
case CodeModel::JITDefault:
@@ -480,10 +480,10 @@ void ARMFrameLowering::emitPrologue(Mach
.setMIFlags(MachineInstr::FrameSetup);
BuildMI(MBB, MBBI, dl, TII.get(ARM::tBLXr))
- .addImm((unsigned)ARMCC::AL).addReg(0)
- .addReg(ARM::R12, RegState::Kill)
- .addReg(ARM::R4, RegState::Implicit)
- .setMIFlags(MachineInstr::FrameSetup);
+ .add(predOps(ARMCC::AL))
+ .addReg(ARM::R12, RegState::Kill)
+ .addReg(ARM::R4, RegState::Implicit)
+ .setMIFlags(MachineInstr::FrameSetup);
break;
}
@@ -684,10 +684,10 @@ void ARMFrameLowering::emitPrologue(Mach
// FIXME: Clarify FrameSetup flags here.
if (RegInfo->hasBasePointer(MF)) {
if (isARM)
- BuildMI(MBB, MBBI, dl,
- TII.get(ARM::MOVr), RegInfo->getBaseRegister())
- .addReg(ARM::SP)
- .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
+ BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), RegInfo->getBaseRegister())
+ .addReg(ARM::SP)
+ .add(predOps(ARMCC::AL))
+ .add(condCodeOp());
else
BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), RegInfo->getBaseRegister())
.addReg(ARM::SP)
@@ -774,7 +774,9 @@ void ARMFrameLowering::emitEpilogue(Mach
// Thumb2 or ARM.
if (isARM)
BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
- .addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
+ .addReg(FramePtr)
+ .add(predOps(ARMCC::AL))
+ .add(condCodeOp());
else
BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
.addReg(FramePtr)
@@ -2150,7 +2152,7 @@ void ARMFrameLowering::adjustForSegmente
BuildMI(McrMBB, DL, TII.get(ARM::MOVr), ScratchReg1)
.addReg(ARM::SP)
.add(predOps(ARMCC::AL))
- .addReg(0);
+ .add(condCodeOp());
}
// sub SR1, sp, #StackSize
@@ -2165,7 +2167,7 @@ void ARMFrameLowering::adjustForSegmente
.addReg(ARM::SP)
.addImm(AlignedStackSize)
.add(predOps(ARMCC::AL))
- .addReg(0);
+ .add(condCodeOp());
}
if (Thumb && ST->isThumb1Only()) {
@@ -2238,7 +2240,7 @@ void ARMFrameLowering::adjustForSegmente
BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ScratchReg0)
.addImm(AlignedStackSize)
.add(predOps(ARMCC::AL))
- .addReg(0);
+ .add(condCodeOp());
}
// Pass second argument for the __morestack by Scratch Register #1.
// The amount size of stack consumed to save function arguments.
@@ -2251,7 +2253,7 @@ void ARMFrameLowering::adjustForSegmente
BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ScratchReg1)
.addImm(alignToARMConstant(ARMFI->getArgumentStackSize()))
.add(predOps(ARMCC::AL))
- .addReg(0);
+ .add(condCodeOp());
}
// push {lr} - Save return address of this function.
Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=292587&r1=292586&r2=292587&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Fri Jan 20 02:15:24 2017
@@ -8603,11 +8603,12 @@ ARMTargetLowering::EmitLowered__chkstk(M
case CodeModel::Default:
case CodeModel::Kernel:
BuildMI(*MBB, MI, DL, TII.get(ARM::tBL))
- .addImm((unsigned)ARMCC::AL).addReg(0)
- .addExternalSymbol("__chkstk")
- .addReg(ARM::R4, RegState::Implicit | RegState::Kill)
- .addReg(ARM::R4, RegState::Implicit | RegState::Define)
- .addReg(ARM::R12, RegState::Implicit | RegState::Define | RegState::Dead);
+ .add(predOps(ARMCC::AL))
+ .addExternalSymbol("__chkstk")
+ .addReg(ARM::R4, RegState::Implicit | RegState::Kill)
+ .addReg(ARM::R4, RegState::Implicit | RegState::Define)
+ .addReg(ARM::R12,
+ RegState::Implicit | RegState::Define | RegState::Dead);
break;
case CodeModel::Large:
case CodeModel::JITDefault: {
@@ -8617,11 +8618,12 @@ ARMTargetLowering::EmitLowered__chkstk(M
BuildMI(*MBB, MI, DL, TII.get(ARM::t2MOVi32imm), Reg)
.addExternalSymbol("__chkstk");
BuildMI(*MBB, MI, DL, TII.get(ARM::tBLXr))
- .addImm((unsigned)ARMCC::AL).addReg(0)
- .addReg(Reg, RegState::Kill)
- .addReg(ARM::R4, RegState::Implicit | RegState::Kill)
- .addReg(ARM::R4, RegState::Implicit | RegState::Define)
- .addReg(ARM::R12, RegState::Implicit | RegState::Define | RegState::Dead);
+ .add(predOps(ARMCC::AL))
+ .addReg(Reg, RegState::Kill)
+ .addReg(ARM::R4, RegState::Implicit | RegState::Kill)
+ .addReg(ARM::R4, RegState::Implicit | RegState::Define)
+ .addReg(ARM::R12,
+ RegState::Implicit | RegState::Define | RegState::Dead);
break;
}
}
@@ -8920,9 +8922,11 @@ ARMTargetLowering::EmitInstrWithCustomIn
// Note: BCC and rsbri will be converted into predicated rsbmi
// by if-conversion pass
BuildMI(*RSBBB, RSBBB->begin(), dl,
- TII->get(isThumb2 ? ARM::t2RSBri : ARM::RSBri), NewRsbDstReg)
- .addReg(ABSSrcReg, ABSSrcKIll ? RegState::Kill : 0)
- .addImm(0).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
+ TII->get(isThumb2 ? ARM::t2RSBri : ARM::RSBri), NewRsbDstReg)
+ .addReg(ABSSrcReg, ABSSrcKIll ? RegState::Kill : 0)
+ .addImm(0)
+ .add(predOps(ARMCC::AL))
+ .add(condCodeOp());
// insert PHI in SinkBB,
// reuse ABSDstReg to not change uses of ABS instruction
Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp?rev=292587&r1=292586&r2=292587&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Fri Jan 20 02:15:24 2017
@@ -707,8 +707,8 @@ MachineInstr *ARMLoadStoreOpt::CreateLoa
.addReg(Base, getKillRegState(KillOldBase));
} else
BuildMI(MBB, InsertBefore, DL, TII->get(ARM::tMOVr), NewBase)
- .addReg(Base, getKillRegState(KillOldBase))
- .addImm(Pred).addReg(PredReg);
+ .addReg(Base, getKillRegState(KillOldBase))
+ .add(predOps(Pred, PredReg));
// The following ADDS/SUBS becomes an update.
Base = NewBase;
@@ -717,19 +717,21 @@ MachineInstr *ARMLoadStoreOpt::CreateLoa
if (BaseOpc == ARM::tADDrSPi) {
assert(Offset % 4 == 0 && "tADDrSPi offset is scaled by 4");
BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase)
- .addReg(Base, getKillRegState(KillOldBase)).addImm(Offset/4)
- .addImm(Pred).addReg(PredReg);
+ .addReg(Base, getKillRegState(KillOldBase))
+ .addImm(Offset / 4)
+ .add(predOps(Pred, PredReg));
} else
BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase)
.add(t1CondCodeOp(true))
.addReg(Base, getKillRegState(KillOldBase))
.addImm(Offset)
- .addImm(Pred)
- .addReg(PredReg);
+ .add(predOps(Pred, PredReg));
} else {
BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase)
- .addReg(Base, getKillRegState(KillOldBase)).addImm(Offset)
- .addImm(Pred).addReg(PredReg).addReg(0);
+ .addReg(Base, getKillRegState(KillOldBase))
+ .addImm(Offset)
+ .add(predOps(Pred, PredReg))
+ .add(condCodeOp());
}
Base = NewBase;
BaseKill = true; // New base is always killed straight away.
@@ -1401,14 +1403,19 @@ bool ARMLoadStoreOpt::MergeBaseUpdateLoa
} else {
int Imm = ARM_AM::getAM2Opc(AddSub, Bytes, ARM_AM::no_shift);
BuildMI(MBB, MBBI, DL, TII->get(NewOpc), MI->getOperand(0).getReg())
- .addReg(Base, RegState::Define)
- .addReg(Base).addReg(0).addImm(Imm).addImm(Pred).addReg(PredReg);
+ .addReg(Base, RegState::Define)
+ .addReg(Base)
+ .addReg(0)
+ .addImm(Imm)
+ .add(predOps(Pred, PredReg));
}
} else {
// t2LDR_PRE, t2LDR_POST
BuildMI(MBB, MBBI, DL, TII->get(NewOpc), MI->getOperand(0).getReg())
- .addReg(Base, RegState::Define)
- .addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg);
+ .addReg(Base, RegState::Define)
+ .addReg(Base)
+ .addImm(Offset)
+ .add(predOps(Pred, PredReg));
}
} else {
MachineOperand &MO = MI->getOperand(0);
@@ -1419,13 +1426,18 @@ bool ARMLoadStoreOpt::MergeBaseUpdateLoa
int Imm = ARM_AM::getAM2Opc(AddSub, Bytes, ARM_AM::no_shift);
// STR_PRE, STR_POST
BuildMI(MBB, MBBI, DL, TII->get(NewOpc), Base)
- .addReg(MO.getReg(), getKillRegState(MO.isKill()))
- .addReg(Base).addReg(0).addImm(Imm).addImm(Pred).addReg(PredReg);
+ .addReg(MO.getReg(), getKillRegState(MO.isKill()))
+ .addReg(Base)
+ .addReg(0)
+ .addImm(Imm)
+ .add(predOps(Pred, PredReg));
} else {
// t2STR_PRE, t2STR_POST
BuildMI(MBB, MBBI, DL, TII->get(NewOpc), Base)
- .addReg(MO.getReg(), getKillRegState(MO.isKill()))
- .addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg);
+ .addReg(MO.getReg(), getKillRegState(MO.isKill()))
+ .addReg(Base)
+ .addImm(Offset)
+ .add(predOps(Pred, PredReg));
}
}
MBB.erase(MBBI);
Modified: llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp?rev=292587&r1=292586&r2=292587&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp Fri Jan 20 02:15:24 2017
@@ -264,10 +264,11 @@ void llvm::emitT2RegPlusImmediate(Machin
if (Fits) {
if (isSub) {
BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg)
- .addReg(BaseReg)
- .addReg(DestReg, RegState::Kill)
- .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
- .setMIFlags(MIFlags);
+ .addReg(BaseReg)
+ .addReg(DestReg, RegState::Kill)
+ .add(predOps(Pred, PredReg))
+ .add(condCodeOp())
+ .setMIFlags(MIFlags);
} else {
// Here we know that DestReg is not SP but we do not
// know anything about BaseReg. t2ADDrr is an invalid
@@ -275,10 +276,11 @@ void llvm::emitT2RegPlusImmediate(Machin
// is fine if SP is the first argument. To be sure we
// do not generate invalid encoding, put BaseReg first.
BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg)
- .addReg(BaseReg)
- .addReg(DestReg, RegState::Kill)
- .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
- .setMIFlags(MIFlags);
+ .addReg(BaseReg)
+ .addReg(DestReg, RegState::Kill)
+ .add(predOps(Pred, PredReg))
+ .add(condCodeOp())
+ .setMIFlags(MIFlags);
}
return;
}
Modified: llvm/trunk/lib/Target/ARM/ThumbRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ThumbRegisterInfo.cpp?rev=292587&r1=292586&r2=292587&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ThumbRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ThumbRegisterInfo.cpp Fri Jan 20 02:15:24 2017
@@ -93,9 +93,10 @@ static void emitThumb2LoadConstPool(Mach
unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
BuildMI(MBB, MBBI, dl, TII.get(ARM::t2LDRpci))
- .addReg(DestReg, getDefRegState(true), SubIdx)
- .addConstantPoolIndex(Idx).addImm((int64_t)ARMCC::AL).addReg(0)
- .setMIFlags(MIFlags);
+ .addReg(DestReg, getDefRegState(true), SubIdx)
+ .addConstantPoolIndex(Idx)
+ .add(predOps(ARMCC::AL))
+ .setMIFlags(MIFlags);
}
/// emitLoadConstPool - Emits a load from constpool to materialize the
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