[PATCH] D28406: [InstCombine] icmp sgt (shl nsw X, C1), C0 --> icmp sgt X, C0 >> C1

[bryant via Phabricator via llvm-commits]

bryant added inline comments.


================
Comment at: lib/Transforms/InstCombine/InstCombineCompares.cpp:1918
+  if (Shl->hasNoSignedWrap()) {
+    if (Cmp.isEquality() || Pred == ICmpInst::ICMP_SGT) {
+      // icmp Pred (shl nsw X, ShiftAmt), C --> icmp Pred X, (C >>s ShiftAmt)
----------------
Just working by analogy (see below), I'm guessing that this isn't true for eq.


https://reviews.llvm.org/D28406