[PATCH] D22398: MIRParser: Allow register class specification on operand

[Phabricator via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL292321: MIRParser: Allow regclass specification on operand (authored by matze).

Changed prior to commit:
  https://reviews.llvm.org/D22398?vs=81808&id=84779#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D22398

Files:
  llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp
  llvm/trunk/lib/CodeGen/MIRParser/MIParser.h
  llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp
  llvm/trunk/test/CodeGen/MIR/AArch64/register-operand-bank.mir
  llvm/trunk/test/CodeGen/MIR/X86/register-operand-class-invalid0.mir
  llvm/trunk/test/CodeGen/MIR/X86/register-operand-class-invalid1.mir
  llvm/trunk/test/CodeGen/MIR/X86/register-operand-class.mir

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