[PATCH] D28782: [AMDGPU] Do not allow register coalescer to create big superregs

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec created this revision.
Herald added a reviewer: tstellarAMD.
Herald added subscribers: tony-tye, yaxunl, nhaehnle, wdng, kzhuravl, arsenm.

Limit register coalescer by not allowing it to artificially increase
size of registers beyond dword. Such super-registers are in fact
register sequences and not distinct HW registers.

With more super-regs we would need to allocate adjacent registers
and constraint regalloc more than needed. Moreover, our super
registers are overlapping. For instance we have VGPR0_VGPR1_VGPR2,
VGPR1_VGPR2_VGPR3, VGPR2_VGPR3_VGPR4 etc, which complicates registers
allocation even more, resulting in excessive spilling.


Repository:
  rL LLVM

https://reviews.llvm.org/D28782

Files:
  lib/Target/AMDGPU/SIRegisterInfo.cpp
  lib/Target/AMDGPU/SIRegisterInfo.h
  test/CodeGen/AMDGPU/half.ll
  test/CodeGen/AMDGPU/limit-coalesce.mir

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D28782.84600.patch
Type: text/x-patch
Size: 4820 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20170116/6612dede/attachment.bin>