[PATCH] D28152: Cortex-A57 scheduling model for ARM backend (AArch32)

[Andrew Zhogin via Phabricator via llvm-commits]

andrew.zhogin updated this revision to Diff 84304.
andrew.zhogin added a comment.

Removed r0px flag and specific cpu. IsR1P0AndLaterPred is now false (vanilla).
Added few scheduling tests.


https://reviews.llvm.org/D28152

Files:
  include/llvm/CodeGen/TargetSchedule.h
  lib/Target/ARM/ARM.td
  lib/Target/ARM/ARMBaseInstrInfo.cpp
  lib/Target/ARM/ARMBaseInstrInfo.h
  lib/Target/ARM/ARMSchedule.td
  lib/Target/ARM/ARMScheduleA57.td
  lib/Target/ARM/ARMScheduleA57WriteRes.td
  test/CodeGen/ARM/cortex-a57-misched-alu.ll
  test/CodeGen/ARM/cortex-a57-misched-basic.ll
  test/CodeGen/ARM/cortex-a57-misched-ldm-wrback.ll
  test/CodeGen/ARM/cortex-a57-misched-ldm.ll
  test/CodeGen/ARM/cortex-a57-misched-stm-wrback.ll
  test/CodeGen/ARM/cortex-a57-misched-stm.ll
  test/CodeGen/ARM/cortex-a57-misched-vfma.ll
  test/CodeGen/ARM/cortex-a57-misched-vldm-wrback.ll
  test/CodeGen/ARM/cortex-a57-misched-vldm.ll
  test/CodeGen/ARM/cortex-a57-misched-vstm-wrback.ll
  test/CodeGen/ARM/cortex-a57-misched-vstm.ll

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