Fwd: NDS32 V3 backend

[Shiva Chen via llvm-commits]

Hi all,

On behalf of Andes Technology Corp,
I am proposing a backend targeting the NDS32 V3 ISA.

NDS32 V3 ISA is a 16/32 bit mixed instruction set architecture that
developed By AndesTech.
You can find more information at the Andes website <http://www.andestech.com/>,
and reference AndeStar ISA Manual (V3 ISA) from document download page
<http://www.andestech.com/product.php?cls=9>.

This is an experimental porting.
Performance-wise, there is still lack target-specific optimization yet.
We focus on the correctness at the begin and definitely need many
reviewers help to point out the right direction.

I split the patch like RISC-V did and hope it could be easier for reviewing.
I have submitted a series of 22 patches implementing code generation
and assembler support.
Please let me know if you'd like to be CCed in or added as a reviewer
to future patches.

Please find the current set of patches for your review here:
* <https://reviews.llvm.org/differential/?authors=shiva0217>

Your reviews and comments are very important to us for making this
contribution better.

Thanks for your time to review our contribution.


Best regards,
Shiva Chen