[PATCH] D28152: Cortex-A57 scheduling model for ARM backend (AArch32)

[James Greenhalgh via Phabricator via llvm-commits]

jgreenhalgh added inline comments.


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Comment at: lib/Target/ARM/ARM.td:783
 
-def : ProcNoItin<"cortex-a57",                          [ARMv8a, ProcA57,
+def : ProcessorModel<"cortex-a57-r0px", CortexA57Model, [ARMv8a, ProcA57,
+                                                         FeatureHWDiv,
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I'm not sure that splitting the option like this is a good idea, certainly this would create an incompatibility with GCC, which does not recognise -mcpu=cortex-a57-r0px. In GCC -mcpu=cortex-a57 enables scheduling for all the optimized instruction pairs (e.g. MOV/MOVT), and uses the r0p0 latency values for the Advanced SIMD multiply accumulate instructions.

In your patch, this extra flag changes the scheduling of vector multiply, multiply accumulate, and the mov/movt instructions. While I can see that this can improve the resulting schedule in some circumstances, my opinion is that fragmenting the option like this is not worth the extra cost of carrying a special option.


https://reviews.llvm.org/D28152