[llvm] r291441 - [SelectionDAG] Fix in legalization of UMAX/SMAX/UMIN/SMIN. Solves PR31486.

[Bjorn Pettersson via llvm-commits]

Author: bjope
Date: Mon Jan  9 06:03:50 2017
New Revision: 291441

URL: http://llvm.org/viewvc/llvm-project?rev=291441&view=rev
Log:
[SelectionDAG] Fix in legalization of UMAX/SMAX/UMIN/SMIN. Solves PR31486.

Summary:
Originally

 i64 = umax t8, Constant:i64<4>

was expanded into

 i32,i32 = umax Constant:i32<0>, Constant:i32<0>
 i32,i32 = umax t7, Constant:i32<4>

Now instead the two produced umax:es return i32 instead of i32, i32.

Thanks to Jan Vesely for help with the test case.

Patch by mikael.holmen at ericsson.com

Reviewers: bogner, jvesely, tstellarAMD, arsenm

Subscribers: test, wdng, RKSimon, arsenm, nhaehnle, llvm-commits

Differential Revision: https://reviews.llvm.org/D28135

Added:
    llvm/trunk/test/CodeGen/AMDGPU/r600-legalize-umax-bug.ll
Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=291441&r1=291440&r2=291441&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Mon Jan  9 06:03:50 2017
@@ -1714,7 +1714,7 @@ void DAGTypeLegalizer::ExpandIntRes_MINM
   EVT CCT = getSetCCResultType(NVT);
 
   // Hi part is always the same op
-  Hi = DAG.getNode(N->getOpcode(), DL, {NVT, NVT}, {LHSH, RHSH});
+  Hi = DAG.getNode(N->getOpcode(), DL, NVT, {LHSH, RHSH});
 
   // We need to know whether to select Lo part that corresponds to 'winning'
   // Hi part or if Hi parts are equal.
@@ -1725,7 +1725,7 @@ void DAGTypeLegalizer::ExpandIntRes_MINM
   SDValue LoCmp = DAG.getSelect(DL, NVT, IsHiLeft, LHSL, RHSL);
 
   // Recursed Lo part if Hi parts are equal, this uses unsigned version
-  SDValue LoMinMax = DAG.getNode(LoOpc, DL, {NVT, NVT}, {LHSL, RHSL});
+  SDValue LoMinMax = DAG.getNode(LoOpc, DL, NVT, {LHSL, RHSL});
 
   Lo = DAG.getSelect(DL, NVT, IsHiEq, LoMinMax, LoCmp);
 }

Added: llvm/trunk/test/CodeGen/AMDGPU/r600-legalize-umax-bug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/r600-legalize-umax-bug.ll?rev=291441&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/r600-legalize-umax-bug.ll (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/r600-legalize-umax-bug.ll Mon Jan  9 06:03:50 2017
@@ -0,0 +1,16 @@
+; RUN: llc -march=r600 -mcpu=cypress -start-after safe-stack %s -o - | FileCheck %s
+; Don't crash
+
+; CHECK: MAX_UINT
+define void @test(i64 addrspace(1)* %out) {
+bb:
+  store i64 2, i64 addrspace(1)* %out
+  %tmp = load i64, i64 addrspace(1)* %out
+  br label %jump
+
+jump:                                             ; preds = %bb
+  %tmp1 = icmp ugt i64 %tmp, 4
+  %umax = select i1 %tmp1, i64 %tmp, i64 4
+  store i64 %umax, i64 addrspace(1)* %out
+  ret void
+}