[PATCH] D27807: [globalisel] Initialize RegisterBanks with static data. Part 1 of 2.

[Daniel Sanders via Phabricator via llvm-commits]

dsanders updated this revision to Diff 83599.
dsanders added a comment.

Updated to account for comments on later patches in the series.

RegisterBank::DataTy has been removed in favour of passing each value to
setRegBankData() and setRegBankCoverage(). RegisterBank::DataTy would have been
removed in https://reviews.llvm.org/D27809 in order to move to a similar initialization style as
TargetRegisterClass so it makes sense to not add it.

https://reviews.llvm.org/D27809 also requested that the finishInit() call that was added be removed.
This call was needed to use the TRI in the initialization of a BitVector but is
not needed by the end of the patch series. I've therefore hardcoded the number
of register classes as 200 and this will be changed in https://reviews.llvm.org/D27338 to be the number
of register classes defined for the target. This shouldn't be a problem since
https://reviews.llvm.org/D27338 already needs to be commited shortly after this patch to minimize the
maintenance burden of the register class tables.

Added the missing printing code to addRegBankCoverage().

This hasn't been rebased to trunk yet.


https://reviews.llvm.org/D27807

Files:
  include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h
  lib/CodeGen/GlobalISel/RegisterBank.cpp
  lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
  lib/Target/AArch64/AArch64RegisterBankInfo.cpp
  lib/Target/ARM/ARMRegisterBankInfo.cpp

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