[PATCH] D28087: X86 instr selection: combine ADDSUB + MUL to FMADDSUB

Vyacheslav Klochkov via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Jan 6 16:42:37 PST 2017


v_klochkov added a comment.

Elena, thank you for the review and for the comments.
I made additional changes accordingly to your recommendations.

Currently, there is no fp_contract bit in FastMathFlags and in SDNodeFlags,
So, the checks used in isFMAddSub() are similar to existing in visitFADDForFMACombine().
That is correct in all situations and there are some bugs for this situation. Perhaps this can be fixed quite soon.
For now I just removed 'fast' attributes from the LIT test.

> You consider the situation when the shuffle is resolved before FMA.
>  But if fadd and fsub are already combined with fmul, fmaddsub will not be created. I'm not sure
>  that this situation is real, except fma are coming form intrinsics ..

if you talk about such pattern:

  t1 = fma <a,b,c>
  t2 = fms <a,b,c>
  shufffle t1,t2,...

That is just a totally different pattern. I don't see how it can be _automatically_ generated now.
If it happen to be generated later and is important to be optimized better, then it can be recognized/optimized, but that would require a separate patch.


https://reviews.llvm.org/D28087





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