[llvm] r291229 - [CostModel][X86] Fix 512-bit SDIV/UDIV 'big' costs.

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Fri Jan  6 05:12:53 2017
New Revision: 291229

URL: http://llvm.org/viewvc/llvm-project?rev=291229&view=rev
Log:
[CostModel][X86] Fix 512-bit SDIV/UDIV 'big' costs.

Set the costs on the lowest target that supports the type.

Modified:
    llvm/trunk/lib/Target/X86/X86TargetTransformInfo.cpp
    llvm/trunk/test/Analysis/CostModel/X86/vdiv-cost.ll

Modified: llvm/trunk/lib/Target/X86/X86TargetTransformInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetTransformInfo.cpp?rev=291229&r1=291228&r2=291229&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86TargetTransformInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86TargetTransformInfo.cpp Fri Jan  6 05:12:53 2017
@@ -226,12 +226,8 @@ int X86TTIImpl::getArithmeticInstrCost(
     // Vectorizing division is a bad idea. See the SSE2 table for more comments.
     { ISD::SDIV,  MVT::v64i8,  64*20 },
     { ISD::SDIV,  MVT::v32i16, 32*20 },
-    { ISD::SDIV,  MVT::v16i32, 16*20 },
-    { ISD::SDIV,  MVT::v8i64,   8*20 },
     { ISD::UDIV,  MVT::v64i8,  64*20 },
-    { ISD::UDIV,  MVT::v32i16, 32*20 },
-    { ISD::UDIV,  MVT::v16i32, 16*20 },
-    { ISD::UDIV,  MVT::v8i64,   8*20 },
+    { ISD::UDIV,  MVT::v32i16, 32*20 }
   };
 
   // Look for AVX512BW lowering tricks for custom cases.
@@ -240,17 +236,23 @@ int X86TTIImpl::getArithmeticInstrCost(
       return LT.first * Entry->Cost;
 
   static const CostTblEntry AVX512CostTable[] = {
-    { ISD::SHL,     MVT::v16i32,    1 },
-    { ISD::SRL,     MVT::v16i32,    1 },
-    { ISD::SRA,     MVT::v16i32,    1 },
-    { ISD::SHL,     MVT::v8i64,     1 },
-    { ISD::SRL,     MVT::v8i64,     1 },
-    { ISD::SRA,     MVT::v8i64,     1 },
+    { ISD::SHL,     MVT::v16i32,     1 },
+    { ISD::SRL,     MVT::v16i32,     1 },
+    { ISD::SRA,     MVT::v16i32,     1 },
+    { ISD::SHL,     MVT::v8i64,      1 },
+    { ISD::SRL,     MVT::v8i64,      1 },
+    { ISD::SRA,     MVT::v8i64,      1 },
 
-    { ISD::MUL,     MVT::v32i8,    13 }, // extend/pmullw/trunc sequence.
-    { ISD::MUL,     MVT::v16i8,     5 }, // extend/pmullw/trunc sequence.
-    { ISD::MUL,     MVT::v16i32,    1 }, // pmulld
-    { ISD::MUL,     MVT::v8i64,     8 }  // 3*pmuludq/3*shift/2*add
+    { ISD::MUL,     MVT::v32i8,     13 }, // extend/pmullw/trunc sequence.
+    { ISD::MUL,     MVT::v16i8,      5 }, // extend/pmullw/trunc sequence.
+    { ISD::MUL,     MVT::v16i32,     1 }, // pmulld
+    { ISD::MUL,     MVT::v8i64,      8 }, // 3*pmuludq/3*shift/2*add
+
+    // Vectorizing division is a bad idea. See the SSE2 table for more comments.
+    { ISD::SDIV,    MVT::v16i32, 16*20 },
+    { ISD::SDIV,    MVT::v8i64,   8*20 },
+    { ISD::UDIV,    MVT::v16i32, 16*20 },
+    { ISD::UDIV,    MVT::v8i64,   8*20 }
   };
 
   if (ST->hasAVX512())

Modified: llvm/trunk/test/Analysis/CostModel/X86/vdiv-cost.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/CostModel/X86/vdiv-cost.ll?rev=291229&r1=291228&r2=291229&view=diff
==============================================================================
--- llvm/trunk/test/Analysis/CostModel/X86/vdiv-cost.ll (original)
+++ llvm/trunk/test/Analysis/CostModel/X86/vdiv-cost.ll Fri Jan  6 05:12:53 2017
@@ -118,7 +118,5 @@ define <16 x i32> @test11(<16 x i32> %a)
 ; CHECK: 'Cost Model Analysis' for function 'test11':
 ; SSE: Found an estimated cost of 320 for instruction:   %div
 ; AVX: Found an estimated cost of 320 for instruction:   %div
-; AVX512F: Found an estimated cost of 48 for instruction:   %div
-; AVX512BW: Found an estimated cost of 320 for instruction:   %div
-; AVX512DQ: Found an estimated cost of 48 for instruction:   %div
-}
+; AVX512: Found an estimated cost of 320 for instruction:   %div
+}