[PATCH] D28198: [X86] Replace AND+IMM64 with SRL/SHL

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a reviewer: RKSimon.
RKSimon added inline comments.


================
Comment at: lib/Target/X86/X86ISelLowering.cpp:15796
+  // number of bits.
+  const int SHIFT_TO_AND_MAX_MASK_WIDTH = 32;
+  const bool ZeroCheck = (X86CC == X86::COND_E || X86CC == X86::COND_NE);
----------------
Bad style
```
const int ShiftToAndMaxMaskWidth = 32;
```


================
Comment at: lib/Target/X86/X86ISelLowering.cpp:15883
+
+        assert(!dyn_cast<ConstantSDNode>(Op0) && "AND node isn't canonicalized");
+        ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op1);
----------------
```
assert(isa<ConstantSDNode>(Op0) && "AND node isn't canonicalized");
```


================
Comment at: lib/Target/X86/X86ISelLowering.cpp:15884
+        assert(!dyn_cast<ConstantSDNode>(Op0) && "AND node isn't canonicalized");
+        ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op1);
+        if (!CN)
----------------
Use auto with casts and dyn_casts


================
Comment at: test/CodeGen/X86/cmp.ll:335
 }
\ No newline at end of file

----------------
Newline


https://reviews.llvm.org/D28198