[PATCH] D28196: [X86] Tune bypassing of slow division for Intel CPUs

[Sanjay Patel via Phabricator via llvm-commits]

spatel added a comment.

Can you update the CHECK lines in both of the test files using utils/update_llc_test_checks.py as a preliminary step ahead of this patch (no review required)? This has 3 benefits:

1. We get tighter checks.
2. It's easier to update the test files for this and future transforms.
3. It's easier to see the diffs induced by this patch.

Note that you'll want to change the RUN lines in atom-bypass-slow-division-64.ll to include a triple ( -mtriple=x86_64-unknown-unknown ) rather than an arch, or you'll probably trigger bot failures.



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Comment at: test/CodeGen/X86/atom-bypass-slow-division-64.ll:3
+; RUN: llc < %s -mcpu=silvermont -march=x86-64 -asm-verbose=false | FileCheck %s
+; RUN: llc < %s -mcpu=skylake    -march=x86-64 -asm-verbose=false | FileCheck %s
 
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Is there some reason to choose skylake here rather than sandybridge? If not, I'd prefer SNB because that's the oldest big core where the feature is applied?


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Comment at: test/CodeGen/X86/slow-div.ll:29-43
 ; Verify that no extra code is generated when optimizing for size.
 
 define i32 @div32_optsize(i32 %a, i32 %b) optsize {
 ; DIV32-LABEL: div32_optsize:
 ; DIV32-NOT: divb
   %div = sdiv i32 %a, %b
   ret i32 %div
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Add an 'optsize' test for the 64-bit divide too?


https://reviews.llvm.org/D28196