[PATCH] D28087: X86 instr selection: combine ADDSUB + MUL to FMADDSUB

Vyacheslav Klochkov via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Dec 29 18:04:54 PST 2016


v_klochkov updated this revision to Diff 82713.
v_klochkov added a comment.

Hi Simon,

Thank you for the code-review.
I simplified the test and added more test cases to it.
BTW, I wanted to add support for 512-bit ADDSUB and FMADDSUB, but then realized that
512-bit ADDSUB operations are not yet defined in *.td files.

I cannot add tests with intrinsic calls like: _mm_mul_ps() + _mm_addsub_ps(),
because addsub intrinsics are lowered too late, much later than mul intrisics.
That problem should be fixed separately:

- IR Dump After Remove unused exception handling info *** ; Function Attrs: nounwind uwtable define <4 x float> @fused_mul_addsub(<4 x float> %a, <4 x float> %b) local_unnamed_addr #0 { entry: %call = call fast fastcc <4 x float> @_mm_mul_ps(<4 x float> %a, <4 x float> %b) %call1 = call fast fastcc <4 x float> @_mm_addsub_ps(<4 x float> %call, <4 x float> %a) ret <4 x float> %call1 }
- IR Dump After Function Integration/Inlining *** ; Function Attrs: nounwind uwtable define <4 x float> @fused_mul_addsub(<4 x float> %a, <4 x float> %b) local_unnamed_addr #0 { entry: %mul.i = fmul fast <4 x float> %b, %a %0 = call fast <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float> %mul.i, <4 x float> %a) #2 ret <4 x float> %0 }

Also, ADDSUB is not generated for _Complex float types.
For some reasons that complex MUL is lowered differently now, 
i.e. real and imaginary parts are computed independently (MUL+FMA for each part).

Hopefully, this patch is just the 1st in a series of patches for improving performance of _Complex MULs and DIVs.

Thank you,
Vyacheslav Klochkov


https://reviews.llvm.org/D28087

Files:
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/CodeGen/X86/fmaddsub-combine.ll

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