[PATCH] D28057: [ARM] Add custom MachineInstr builder. NFC.

[Diana Picus via Phabricator via llvm-commits]

rovka created this revision.
rovka added reviewers: MatzeB, t.p.northover, jmolloy, kristof.beyls.
rovka added subscribers: llvm-commits, rengolin.
Herald added a subscriber: aemerson.

Add a subclass of MIBuilderBase for the ARM backend. This should allow us to get
rid of the AddDefaultPred, AddDefaultCC etc helpers and have a cleaner interface
instead.

This patch doesn't remove uses of the helpers, but it contains an example of how
to use the new builder in the ARM backend. A more thorough cleanup will follow
in other patches.


https://reviews.llvm.org/D28057

Files:
  lib/Target/ARM/ARMBaseInstrInfo.cpp
  lib/Target/ARM/ARMBaseInstrInfo.h
  lib/Target/ARM/ARMInstrBuilder.h


Index: lib/Target/ARM/ARMInstrBuilder.h
===================================================================
--- /dev/null
+++ lib/Target/ARM/ARMInstrBuilder.h
@@ -0,0 +1,38 @@
+//===-- ARMInstrBuilder.h - Simplify creation of ARM insts ------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains a special instruction builder for ARM, which provides
+// functionality for handling special ARM operands such as predicates and CC.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_ARM_ARMINSTRBUILDER_H
+#define LLVM_LIB_TARGET_ARM_ARMINSTRBUILDER_H
+
+#include "MCTargetDesc/ARMBaseInfo.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+
+namespace llvm {
+
+class ARMInstrBuilder : public MIBuilderBase<ARMInstrBuilder> {
+public:
+  using MIBuilderBase<ARMInstrBuilder>::MIBuilderBase;
+
+  const ARMInstrBuilder &addPred(ARMCC::CondCodes Pred = ARMCC::AL,
+                                 unsigned PredReg = 0) const {
+    return addImm(static_cast<int64_t>(Pred)).addReg(PredReg);
+  }
+
+  const ARMInstrBuilder &addCC(unsigned CCReg = 0) const {
+    return addReg(CCReg);
+  }
+};
+} // End llvm namespace
+
+#endif
Index: lib/Target/ARM/ARMBaseInstrInfo.h
===================================================================
--- lib/Target/ARM/ARMBaseInstrInfo.h
+++ lib/Target/ARM/ARMBaseInstrInfo.h
@@ -401,6 +401,7 @@
   bool isSwiftFastImmShift(const MachineInstr *MI) const;
 };
 
+// FIXME: Remove these when all uses are gone
 static inline
 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
   return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
Index: lib/Target/ARM/ARMBaseInstrInfo.cpp
===================================================================
--- lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -17,13 +17,13 @@
 #include "ARMConstantPoolValue.h"
 #include "ARMFeatures.h"
 #include "ARMHazardRecognizer.h"
+#include "ARMInstrBuilder.h"
 #include "ARMMachineFunctionInfo.h"
 #include "MCTargetDesc/ARMAddressingModes.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/CodeGen/LiveVariables.h"
 #include "llvm/CodeGen/MachineConstantPool.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
-#include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineJumpTableInfo.h"
 #include "llvm/CodeGen/MachineMemOperand.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
@@ -164,13 +164,13 @@
         // Can't encode it in a so_imm operand. This transformation will
         // add more than 1 instruction. Abandon!
         return nullptr;
-      UpdateMI = BuildMI(MF, MI.getDebugLoc(),
-                         get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
-                     .addReg(BaseReg)
-                     .addImm(Amt)
-                     .addImm(Pred)
-                     .addReg(0)
-                     .addReg(0);
+      UpdateMI =
+          BuildMI<ARMInstrBuilder>(MF, MI.getDebugLoc(),
+                                   get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
+              .addReg(BaseReg)
+              .addImm(Amt)
+              .addPred(Pred)
+              .addCC();
     } else if (Amt != 0) {
       ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
       unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);


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