[llvm] r290299 - AMDGPU: Update isFPImmLegal for f16

[Matt Arsenault via llvm-commits]

Author: arsenm
Date: Wed Dec 21 21:05:30 2016
New Revision: 290299

URL: http://llvm.org/viewvc/llvm-project?rev=290299&view=rev
Log:
AMDGPU: Update isFPImmLegal for f16

I don't think this matters because ConstantFP is legal.

Modified:
    llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp?rev=290299&r1=290298&r2=290299&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp Wed Dec 21 21:05:30 2016
@@ -498,7 +498,8 @@ bool AMDGPUTargetLowering::isSelectSuppo
 // FIXME: Why are we reporting vectors of FP immediates as legal?
 bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
   EVT ScalarVT = VT.getScalarType();
-  return (ScalarVT == MVT::f32 || ScalarVT == MVT::f64);
+  return (ScalarVT == MVT::f32 || ScalarVT == MVT::f64 ||
+         (ScalarVT == MVT::f16 && Subtarget->has16BitInsts()));
 }
 
 // We don't want to shrink f64 / f32 constants.