[PATCH] D27880: DAG: Don't fold vector extract into load if target doesn't want to

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added a subscriber: llvm-commits.
Herald added a reviewer: tstellarAMD.
Herald added subscribers: nhaehnle, wdng.

Fixes turning a 32-bit scalar load into an extending vector load
for AMDGPU when dynamically indexing a vector.


https://reviews.llvm.org/D27880

Files:
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  test/CodeGen/AMDGPU/extract_vector_elt-i16.ll


Index: test/CodeGen/AMDGPU/extract_vector_elt-i16.ll
===================================================================
--- test/CodeGen/AMDGPU/extract_vector_elt-i16.ll
+++ test/CodeGen/AMDGPU/extract_vector_elt-i16.ll
@@ -15,6 +15,34 @@
   ret void
 }
 
+; GCN-LABEL: {{^}}extract_vector_elt_v2i16_dynamic_sgpr:
+; GCN: s_load_dword [[VEC:s[0-9]+]]
+; GCN: s_load_dword [[IDX:s[0-9]+]]
+; GCN: s_lshr_b32 s{{[0-9]+}}, [[IDX]], 16
+; GCN: v_mov_b32_e32 [[VVEC:v[0-9]+]], [[VEC]]
+define void @extract_vector_elt_v2i16_dynamic_sgpr(i16 addrspace(1)* %out, <2 x i16> addrspace(2)* %vec.ptr, i32 %idx) #0 {
+  %vec = load <2 x i16>, <2 x i16> addrspace(2)* %vec.ptr
+  %elt = extractelement <2 x i16> %vec, i32 %idx
+  store i16 %elt, i16 addrspace(1)* %out, align 2
+  ret void
+}
+
+; GCN-LABEL: {{^}}extract_vector_elt_v2i16_dynamic_vgpr:
+; GCN: {{buffer|flat}}_load_dword [[IDX:v[0-9]+]]
+; GCN: buffer_load_dword [[VEC:v[0-9]+]]
+; GCN: v_lshrrev_b32_e32 [[ELT:v[0-9]+]], 16, [[VEC]]
+define void @extract_vector_elt_v2i16_dynamic_vgpr(i16 addrspace(1)* %out, <2 x i16> addrspace(1)* %vec.ptr, i32 addrspace(1)* %idx.ptr) #0 {
+  %tid = call i32 @llvm.amdgcn.workitem.id.x()
+  %tid.ext = sext i32 %tid to i64
+  %gep = getelementptr inbounds i32, i32 addrspace(1)* %idx.ptr, i64 %tid.ext
+  %out.gep = getelementptr inbounds i16, i16 addrspace(1)* %out, i64 %tid.ext
+  %idx = load volatile i32, i32 addrspace(1)* %gep
+  %vec = load <2 x i16>, <2 x i16> addrspace(1)* %vec.ptr
+  %elt = extractelement <2 x i16> %vec, i32 %idx
+  store i16 %elt, i16 addrspace(1)* %out.gep, align 2
+  ret void
+}
+
 ; GCN-LABEL: {{^}}extract_vector_elt_v3i16:
 ; GCN: buffer_load_ushort
 ; GCN: buffer_store_short
@@ -80,4 +108,7 @@
   ret void
 }
 
+declare i32 @llvm.amdgcn.workitem.id.x() #1
+
 attributes #0 = { nounwind }
+attributes #1 = { nounwind readnone }
Index: lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -12552,6 +12552,11 @@
   if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VecEltVT))
     return SDValue();
 
+  ISD::LoadExtType ExtTy = ResultVT.bitsGT(VecEltVT) ?
+    ISD::NON_EXTLOAD : ISD::EXTLOAD;
+  if (!TLI.shouldReduceLoadWidth(OriginalLoad, ExtTy, VecEltVT))
+    return SDValue();
+
   Align = NewAlign;
 
   SDValue NewPtr = OriginalLoad->getBasePtr();


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