[llvm] r289844 - [AArch64][GlobalISel] Remove redundant RBI comments. NFC.
Ahmed Bougacha via llvm-commits
llvm-commits at lists.llvm.org
Thu Dec 15 10:22:15 PST 2016
Date: Thu Dec 15 12:22:15 2016
New Revision: 289844
[AArch64][GlobalISel] Remove redundant RBI comments. NFC.
It's brittle, and Doxygen already picks the overriden method's comment
--- llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.h (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.h Thu Dec 15 12:22:15 2016
@@ -50,32 +50,13 @@ class AArch64RegisterBankInfo final : pu
AArch64RegisterBankInfo(const TargetRegisterInfo &TRI);
- /// Get the cost of a copy from \p B to \p A, or put differently,
- /// get the cost of A = COPY B. Since register banks may cover
- /// different size, \p Size specifies what will be the size in bits
- /// that will be copied around.
- /// \note Since this is a copy, both registers have the same size.
unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
unsigned Size) const override;
- /// Get a register bank that covers \p RC.
- /// \pre \p RC is a user-defined register class (as opposed as one
- /// generated by TableGen).
- /// \note The mapping RC -> RegBank could be built while adding the
- /// coverage for the register banks. However, we do not do it, because,
- /// at least for now, we only need this information for register classes
- /// that are used in the description of instruction. In other words,
- /// there are just a handful of them and we do not want to waste space.
- /// \todo This should be TableGen'ed.
const RegisterBank &
getRegBankFromRegClass(const TargetRegisterClass &RC) const override;
- /// Get the alternative mappings for \p MI.
- /// Alternative in the sense different from getInstrMapping.
getInstrAlternativeMappings(const MachineInstr &MI) const override;
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