[PATCH] D27774: [ARM] Implement isExtractSubvectorCheap

[Eli Friedman via Phabricator via llvm-commits]

efriedma created this revision.
efriedma added reviewers: rengolin, t.p.northover, jmolloy.
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See https://reviews.llvm.org/D6678 for the history of isExtractSubvectorCheap.  Essentially the same considerations apply to ARM.

This temporarily breaks the formation of vpadd/vpaddl in certain cases; AddCombineToVPADDL essentially assumes that we won't form VUZP shuffles.  This is mostly orthogonal, though, so I'll fix it in a followup.


Repository:
  rL LLVM

https://reviews.llvm.org/D27774

Files:
  lib/Target/ARM/ARMISelLowering.cpp
  lib/Target/ARM/ARMISelLowering.h
  test/CodeGen/ARM/vext.ll
  test/CodeGen/ARM/vpadd.ll
  test/CodeGen/ARM/vuzp.ll
  test/CodeGen/ARM/vzip.ll

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