[PATCH] D27624: [ARM] Split 128-bit vectors in BUILD_VECTOR lowering
Eli Friedman via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 14 10:40:02 PST 2016
efriedma added inline comments.
Comment at: lib/Target/ARM/ARMISelLowering.cpp:6232
+ Upper = LowerBUILD_VECTOR(Upper, DAG, ST);
+ if (Lower && Upper)
+ return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lower, Upper);
> I'm assuming `LowerBUILD_VECTOR` can return `SDNode()` if there's no need for it, thus the concat only happening if both were lowered.
> Is this is your strategy around "we might discover a better way to lower it"?
> How can we avoid cases where it doesn't?
LowerBUILD_VECTOR can return SDNode() in some cases... I think in practice, though, it only fails for splats and constants.
Mostly, I'm just depending on the fact that the worst case isn't any worse than what we would do anyway; a series of INSERT_VECTOR_ELT operations on two 64-bit vectors is roughly equivalent to a series of INSERT_VECTOR_ELT operations on one 128-bit vector.
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