[PATCH] D27761: [Thumb] Teach ISel how to lower compares of AND bitmasks efficiently

Sjoerd Meijer via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Dec 14 08:55:04 PST 2016

SjoerdMeijer created this revision.
SjoerdMeijer added reviewers: jmolloy, mehdi_amini, rengolin, t.p.northover.
SjoerdMeijer added a subscriber: llvm-commits.

This is recommit of r285893, but with a correctness fix. The problem of the original commit was that this:

bic	r5, r7, #31
cbz	r5, .LBB2_10

got rewritten into:

lsrs	r5, r7, #5
beq	.LBB2_10

The result in destination register r5 is not the same, and this is incorrect when r5 is not dead. So the fix includes checking the uses of the AND destination register.

For completeness, this was the original commit message:

For the common pattern (CMPZ (AND x, #bitmask), #0), we can do some more efficient instruction selection if the bitmask is one consecutive sequence of set bits (32 - clz(bm) - ctz(bm) == popcount(bm)).

1. If the bitmask touches the LSB, then we can remove all the upper bits and set the flags by doing one LSLS.
2. If the bitmask touches the MSB, then we can remove all the lower bits and set the flags with one LSRS.
3. If the bitmask has popcount == 1 (only one set bit), we can shift that bit into the sign bit with one LSLS and change the condition query from NE/EQ to MI/PL (we could also implement this by shifting into the carry bit and branching on BCC/BCS).
4. Otherwise, we can emit a sequence of LSLS+LSRS to remove the upper and lower zero bits of the mask.

1-3 require only one 16-bit instruction and can elide the CMP. 4 requires two 16-bit instructions but can elide the CMP and doesn't require materializing a complex immediate, so is also a win.



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