[PATCH] D27694: [ARM] Add ARMISD::VLD1DUP to match vld1_dup more consistently
Eli Friedman via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 12 18:02:04 PST 2016
efriedma created this revision.
efriedma added reviewers: t.p.northover, jmolloy.
efriedma added subscribers: llvm-commits, grosbach, bob.wilson.
efriedma set the repository for this revision to rL LLVM.
Herald added subscribers: rengolin, aemerson.
Currently, there are substantial problems forming vld1_dup even if the
VDUP survives legalization. The lack of an actual node
leads to terrible results: not only can we not form post-increment vld1_dup
instructions, but we form scalar pre-increment and post-increment
loads which force the loaded value into a GPR. This patch fixes that
by combining the vdup+load into an ARMISD node before DAGCombine
messes it up.
Also includes a crash fix for vld2_dup (see testcase @vld2dupi8_postinc_variable).
Not sure who to ask to review this...
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