[PATCH] D27677: [AArch64] Add feature for disabling unaligned quadword store penalty
Matthias Braun via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 12 11:11:23 PST 2016
MatzeB added a comment.
In https://reviews.llvm.org/D27677#620131, @mssimpso wrote:
> In https://reviews.llvm.org/D27677#620116, @MatzeB wrote:
> > Isn't this the same as "FeatureSlowMisaligned128Store"?
> I wasn't aware of this, thanks! It looks like Cyclone is the only subtarget that sets FeatureSlowMisaligned128Store at the moment. To preserve existing behavior for all subtargets (except Kryo and Falkor), should we also set this feature for the others?
If you set it for most of the other CPUs then you will change behavior of AArch64TargetLowering::allowsMisalignedMemoryAccesses() and that performStoreCombine() thing. It may very well be one of the many artifacts showing that the aarch64 target was initially designed for cyclone, however someone working on the other ARM chips should comment on that.
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