[llvm] r289336 - [X86][SSE] Move ZeroVector creation into the shuffle pattern case where its actually used.

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Sat Dec 10 13:49:55 2016
New Revision: 289336

URL: http://llvm.org/viewvc/llvm-project?rev=289336&view=rev
Log:
[X86][SSE] Move ZeroVector creation into the shuffle pattern case where its actually used.

Also fix the ZeroVector's type - I've no idea how this hasn't caused problems........

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=289336&r1=289335&r2=289336&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sat Dec 10 13:49:55 2016
@@ -11071,8 +11071,6 @@ static SDValue lowerV16I8VectorShuffle(c
     if (Mask[i] >= 0)
       (i < 8 ? LoBlendMask[i] : HiBlendMask[i % 8]) = Mask[i];
 
-  SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
-
   SDValue VLoHalf, VHiHalf;
   // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
   // them out and avoid using UNPCK{L,H} to extract the elements of V as
@@ -11097,6 +11095,8 @@ static SDValue lowerV16I8VectorShuffle(c
   } else {
     // Otherwise just unpack the low half of V into VLoHalf and the high half into
     // VHiHalf so that we can blend them as i16s.
+    SDValue Zero = getZeroVector(MVT::v16i8, Subtarget, DAG, DL);
+
     VLoHalf = DAG.getBitcast(
         MVT::v8i16, DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
     VHiHalf = DAG.getBitcast(