[PATCH] D27644: Bail out for reduceVMULWidth for illegal types

[Wei Mi via Phabricator via llvm-commits]

wmi created this revision.
wmi added reviewers: mkuper, RKSimon.
wmi added a subscriber: llvm-commits.
wmi set the repository for this revision to rL LLVM.

This is a temp workaround for PR31323. I will come up a following patch to address illegal types better.


Repository:
  rL LLVM

https://reviews.llvm.org/D27644

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/shrink_vmul_illtype.ll


Index: test/CodeGen/X86/shrink_vmul_illtype.ll
===================================================================
--- test/CodeGen/X86/shrink_vmul_illtype.ll
+++ test/CodeGen/X86/shrink_vmul_illtype.ll
@@ -0,0 +1,24 @@
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2
+; PR31323: reduceVMULWidth doesn't handle illegal vector types like <3 x i8> or <5 x i16> correctly.
+; For now, give up if such illegal vector types are seen.
+
+ at c = external global i32*, align 8
+
+define void @mul_3xi8(i8* nocapture readonly %a, i8* nocapture readonly %b, i64 %index) {
+entry:
+  %pre = load i32*, i32** @c
+  %tmp6 = getelementptr inbounds i8, i8* %a, i64 %index
+  %tmp7 = bitcast i8* %tmp6 to <3 x i8>*
+  %wide.load = load <3 x i8>, <3 x i8>* %tmp7, align 1
+  %tmp8 = zext <3 x i8> %wide.load to <3 x i32>
+  %tmp10 = getelementptr inbounds i8, i8* %b, i64 %index
+  %tmp11 = bitcast i8* %tmp10 to <3 x i8>*
+  %wide.load17 = load <3 x i8>, <3 x i8>* %tmp11, align 1
+  %tmp12 = zext <3 x i8> %wide.load17 to <3 x i32>
+  %tmp13 = mul nuw nsw <3 x i32> %tmp12, %tmp8
+  %tmp14 = getelementptr inbounds i32, i32* %pre, i64 %index
+  %tmp15 = bitcast i32* %tmp14 to <3 x i32>*
+  store <3 x i32> %tmp13, <3 x i32>* %tmp15, align 4
+  ret void
+}
+
Index: lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- lib/Target/X86/X86ISelLowering.cpp
+++ lib/Target/X86/X86ISelLowering.cpp
@@ -29327,6 +29327,12 @@
   MVT OpsVT = MVT::getVectorVT(MVT::i16, RegSize / 16);
   EVT ReducedVT =
       EVT::getVectorVT(*DAG.getContext(), MVT::i16, VT.getVectorNumElements());
+
+  // FIXME: Type like 3 x i8 cannot be properly handled. Bail out here to
+  // workaround the bug. It should be fixed soon in a following patch.
+  if (RegSize % ReducedVT.getSizeInBits() != 0)
+    return SDValue();
+
   // Shrink the operands of mul.
   SDValue NewN0 = DAG.getNode(ISD::TRUNCATE, DL, ReducedVT, N0);
   SDValue NewN1 = DAG.getNode(ISD::TRUNCATE, DL, ReducedVT, N1);


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