[PATCH] D27624: [ARM] Split 128-bit vectors in BUILD_VECTOR lowering

[Eli Friedman via Phabricator via llvm-commits]

efriedma created this revision.
efriedma added reviewers: ab, t.p.northover, jmolloy.
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Herald added subscribers: rengolin, aemerson.

Given that INSERT_VECTOR_ELT operates on D registers anyway, combining 64-bit vectors into a 128-bit vector is basically free.  Therefore, try to split BUILD_VECTOR nodes before giving up and lowering them to a series of INSERT_VECTOR_ELT instructions.  Sometimes this allows dramatically better lowerings; see testcases for examples.  Inspired by similar code in the x86 backend for AVX.

For the @vcombine_vdup, I'm not happy with the DAGCombine transforms which produce a BUILD_VECTOR in the first place; we're taking splat shuffles which were carefully preserved in the IR, and destroying them in DAGCombine by transforming concat_vec(splat(a), splat(a)) -> concat_vec(build_vector(a,a,a,a), build_vector(b,b,b,b)) -> build_vector(a,a,a,a,b,b,b,b).  Maybe we could improve this somehow?


Repository:
  rL LLVM

https://reviews.llvm.org/D27624

Files:
  lib/Target/ARM/ARMISelLowering.cpp
  test/CodeGen/ARM/big-endian-vector-callee.ll
  test/CodeGen/ARM/vcombine.ll
  test/CodeGen/ARM/vext.ll
  test/CodeGen/ARM/vtrn.ll

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