[llvm] r289191 - [AVR] Add tests for a large number of pseudo instructions
Dylan McKay via llvm-commits
llvm-commits at lists.llvm.org
Thu Dec 8 23:49:05 PST 2016
Author: dylanmckay
Date: Fri Dec 9 01:49:04 2016
New Revision: 289191
URL: http://llvm.org/viewvc/llvm-project?rev=289191&view=rev
Log:
[AVR] Add tests for a large number of pseudo instructions
This adds MIR tests for 24 pseudo instructions.
Added:
llvm/trunk/test/CodeGen/AVR/pseudo/ASRWRd.mir
llvm/trunk/test/CodeGen/AVR/pseudo/FRMIDX.mir
llvm/trunk/test/CodeGen/AVR/pseudo/INWRdA.mir
llvm/trunk/test/CodeGen/AVR/pseudo/LDIWRdK.mir
llvm/trunk/test/CodeGen/AVR/pseudo/LDSWRdK.mir
llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtr.mir
llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir
llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir
llvm/trunk/test/CodeGen/AVR/pseudo/LPMWRdZ.mir
llvm/trunk/test/CodeGen/AVR/pseudo/LPMWRdZPi.mir
llvm/trunk/test/CodeGen/AVR/pseudo/LSLWRd.mir
llvm/trunk/test/CodeGen/AVR/pseudo/LSRWRd.mir
llvm/trunk/test/CodeGen/AVR/pseudo/OUTWARr.mir
llvm/trunk/test/CodeGen/AVR/pseudo/POPWRd.mir
llvm/trunk/test/CodeGen/AVR/pseudo/PUSHWRr.mir
llvm/trunk/test/CodeGen/AVR/pseudo/ROLWRd.mir
llvm/trunk/test/CodeGen/AVR/pseudo/RORWRd.mir
llvm/trunk/test/CodeGen/AVR/pseudo/SEXT.mir
llvm/trunk/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir
llvm/trunk/test/CodeGen/AVR/pseudo/STSWKRr.mir
llvm/trunk/test/CodeGen/AVR/pseudo/STWPtrPdRr.mir
llvm/trunk/test/CodeGen/AVR/pseudo/STWPtrPiRr.mir
llvm/trunk/test/CodeGen/AVR/pseudo/STWPtrRr.mir
llvm/trunk/test/CodeGen/AVR/pseudo/ZEXT.mir
Modified:
llvm/trunk/lib/Target/AVR/AVRExpandPseudoInsts.cpp
llvm/trunk/test/CodeGen/AVR/progmem-extended.ll
llvm/trunk/test/CodeGen/AVR/pseudo/CPCWRdRr.mir
llvm/trunk/test/CodeGen/AVR/pseudo/CPWRdRr.mir
Modified: llvm/trunk/lib/Target/AVR/AVRExpandPseudoInsts.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AVR/AVRExpandPseudoInsts.cpp?rev=289191&r1=289190&r2=289191&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AVR/AVRExpandPseudoInsts.cpp (original)
+++ llvm/trunk/lib/Target/AVR/AVRExpandPseudoInsts.cpp Fri Dec 9 01:49:04 2016
@@ -703,6 +703,16 @@ bool AVRExpandPseudo::expand<AVR::LDDWRd
return true;
}
+template <>
+bool AVRExpandPseudo::expand<AVR::LPMWRdZ>(Block &MBB, BlockIt MBBI) {
+ llvm_unreachable("wide LPM is unimplemented");
+}
+
+template <>
+bool AVRExpandPseudo::expand<AVR::LPMWRdZPi>(Block &MBB, BlockIt MBBI) {
+ llvm_unreachable("wide LPMPi is unimplemented");
+}
+
template<typename Func>
bool AVRExpandPseudo::expandAtomic(Block &MBB, BlockIt MBBI, Func f) {
// Remove the pseudo instruction.
@@ -1415,6 +1425,8 @@ bool AVRExpandPseudo::expandMI(Block &MB
EXPAND(AVR::LDWRdPtrPd);
case AVR::LDDWRdYQ: //:FIXME: remove this once PR13375 gets fixed
EXPAND(AVR::LDDWRdPtrQ);
+ EXPAND(AVR::LPMWRdZ);
+ EXPAND(AVR::LPMWRdZPi);
EXPAND(AVR::AtomicLoad8);
EXPAND(AVR::AtomicLoad16);
EXPAND(AVR::AtomicStore8);
Modified: llvm/trunk/test/CodeGen/AVR/progmem-extended.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/progmem-extended.ll?rev=289191&r1=289190&r2=289191&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/progmem-extended.ll (original)
+++ llvm/trunk/test/CodeGen/AVR/progmem-extended.ll Fri Dec 9 01:49:04 2016
@@ -1,4 +1,7 @@
; RUN: llc < %s -march=avr -mattr=movw,lpmx | FileCheck %s
+; XFAIL: *
+
+# Wide LPM is currently unimplemented in the pseudo expansion pass.
; Tests the extended LPM instructions (LPMW, LPM Rd, Z+).
Added: llvm/trunk/test/CodeGen/AVR/pseudo/ASRWRd.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/ASRWRd.mir?rev=289191&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/ASRWRd.mir (added)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/ASRWRd.mir Fri Dec 9 01:49:04 2016
@@ -0,0 +1,22 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+
+--- |
+ target triple = "avr--"
+ define void @test() {
+ entry:
+ ret void
+ }
+...
+
+---
+name: test
+body: |
+ bb.0.entry:
+
+ ; CHECK-LABEL: test
+
+ ; CHECK: %r15 = ASRRd %r15, implicit-def %sreg
+ ; CHECK-NEXT: %r14 = RORRd %r14, implicit-def %sreg, implicit killed %sreg
+
+ %r15r14 = ASRWRd %r15r14, implicit-def %sreg
+...
Modified: llvm/trunk/test/CodeGen/AVR/pseudo/CPCWRdRr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/CPCWRdRr.mir?rev=289191&r1=289190&r2=289191&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/CPCWRdRr.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/CPCWRdRr.mir Fri Dec 9 01:49:04 2016
@@ -1,5 +1,4 @@
# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
-# XFAIL: *
# This test checks the expansion of the 16-bit CPCW pseudo instruction.
@@ -18,5 +17,8 @@ body: |
; CHECK-LABEL: test_cpcwrdrr
- %r15r14 = CPCWRdRr %r15r14, %r21r20, implicit-def %sreg, implicit %sreg
+ ; CHECK: CPCRdRr %r20, %r22, implicit-def %sreg, implicit killed %sreg
+ ; CHECK-NEXT: CPCRdRr %r21, %r23, implicit-def %sreg, implicit killed %sreg
+
+ CPCWRdRr %r21r20, %r23r22, implicit-def %sreg, implicit %sreg
...
Modified: llvm/trunk/test/CodeGen/AVR/pseudo/CPWRdRr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/CPWRdRr.mir?rev=289191&r1=289190&r2=289191&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/CPWRdRr.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/CPWRdRr.mir Fri Dec 9 01:49:04 2016
@@ -1,5 +1,4 @@
# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
-# XFAIL: *
# This test checks the expansion of the 16-bit CPW pseudo instruction.
@@ -18,5 +17,8 @@ body: |
; CHECK-LABEL: test_cpwrdrr
- %r15r14 = CPWRdRr %r15r14, %r21r20, implicit-def %sreg
+ ; CHECK: CPRdRr %r14, %r20, implicit-def %sreg
+ ; CHECK-NEXT: CPCRdRr %r15, %r21, implicit-def %sreg, implicit killed %sreg
+
+ CPWRdRr %r15r14, %r21r20, implicit-def %sreg
...
Added: llvm/trunk/test/CodeGen/AVR/pseudo/FRMIDX.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/FRMIDX.mir?rev=289191&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/FRMIDX.mir (added)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/FRMIDX.mir Fri Dec 9 01:49:04 2016
@@ -0,0 +1,25 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+
+# TODO: Write this test.
+# This instruction isn't expanded by the pseudo expansion passs, but
+# rather AVRRegisterInfo::eliminateFrameIndex.
+
+--- |
+ target triple = "avr--"
+ define void @test() {
+ entry:
+ ret void
+ }
+...
+
+---
+name: test
+registers:
+ - { id: 0, class: _ }
+body: |
+ bb.0.entry:
+
+ ; CHECK-LABEL: test
+
+ %r29r28 = FRMIDX %r31r30, 0, implicit-def %sreg
+...
Added: llvm/trunk/test/CodeGen/AVR/pseudo/INWRdA.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/INWRdA.mir?rev=289191&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/INWRdA.mir (added)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/INWRdA.mir Fri Dec 9 01:49:04 2016
@@ -0,0 +1,22 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+
+--- |
+ target triple = "avr--"
+ define void @test() {
+ entry:
+ ret void
+ }
+...
+
+---
+name: test
+body: |
+ bb.0.entry:
+
+ ; CHECK-LABEL: test
+
+ ; CHECK: %r14 = INRdA 31
+ ; CHECK-NEXT: %r15 = INRdA 32
+
+ %r15r14 = INWRdA 31
+...
Added: llvm/trunk/test/CodeGen/AVR/pseudo/LDIWRdK.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/LDIWRdK.mir?rev=289191&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/LDIWRdK.mir (added)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/LDIWRdK.mir Fri Dec 9 01:49:04 2016
@@ -0,0 +1,24 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+
+# This test checks the expansion of the 16-bit LDIWRdK pseudo instruction.
+
+--- |
+ target triple = "avr--"
+ define void @test_ldiwrdrr() {
+ entry:
+ ret void
+ }
+...
+
+---
+name: test_ldiwrdrr
+body: |
+ bb.0.entry:
+
+ ; CHECK-LABEL: test_ldiwrdrr
+
+ ; CHECK: %r30 = LDIRdK 255
+ ; CHECK-NEXT: %r31 = LDIRdK 9
+
+ %r31r30 = LDIWRdK 2559
+...
Added: llvm/trunk/test/CodeGen/AVR/pseudo/LDSWRdK.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/LDSWRdK.mir?rev=289191&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/LDSWRdK.mir (added)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/LDSWRdK.mir Fri Dec 9 01:49:04 2016
@@ -0,0 +1,24 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+
+# This test checks the expansion of the 16-bit LDSWRdK pseudo instruction.
+
+--- |
+ target triple = "avr--"
+ define void @test_ldswrdrr() {
+ entry:
+ ret void
+ }
+...
+
+---
+name: test_ldswrdrr
+body: |
+ bb.0.entry:
+
+ ; CHECK-LABEL: test_ldswrdrr
+
+ ; CHECK: %r30 = LDSRdK 2559
+ ; CHECK-NEXT: %r31 = LDSRdK 2560
+
+ %r31r30 = LDSWRdK 2559
+...
Added: llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtr.mir?rev=289191&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtr.mir (added)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtr.mir Fri Dec 9 01:49:04 2016
@@ -0,0 +1,24 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+
+# This test checks the expansion of the 16-bit LDWRdPtr pseudo instruction.
+
+--- |
+ target triple = "avr--"
+ define void @test_ldwrdptr() {
+ entry:
+ ret void
+ }
+...
+
+---
+name: test_ldwrdptr
+body: |
+ bb.0.entry:
+
+ ; CHECK-LABEL: test_ldwrdptr
+
+ ; CHECK: %r0 = LDRdPtr %r31r30
+ ; CHECK-NEXT: early-clobber %r1 = LDDRdPtrQ %r31r30, 1
+
+ %r1r0 = LDWRdPtr %r31r30
+...
Added: llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir?rev=289191&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir (added)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir Fri Dec 9 01:49:04 2016
@@ -0,0 +1,24 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+
+# This test checks the expansion of the 16-bit LDWRdPtrPd pseudo instruction.
+
+--- |
+ target triple = "avr--"
+ define void @test_ldwrdptrpd() {
+ entry:
+ ret void
+ }
+...
+
+---
+name: test_ldwrdptrpd
+body: |
+ bb.0.entry:
+
+ ; CHECK-LABEL: test_ldwrdptrpd
+
+ ; CHECK: early-clobber %r1, early-clobber %r31r30 = LDRdPtrPd killed %r31r30
+ ; CHECK-NEXT: early-clobber %r0, early-clobber %r31r30 = LDRdPtrPd killed %r31r30
+
+ %r1r0, %r31r30 = LDWRdPtrPd %r31r30
+...
Added: llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir?rev=289191&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir (added)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir Fri Dec 9 01:49:04 2016
@@ -0,0 +1,24 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+
+# This test checks the expansion of the 16-bit LDWRdPtrPi pseudo instruction.
+
+--- |
+ target triple = "avr--"
+ define void @test_ldwrdptrpi() {
+ entry:
+ ret void
+ }
+...
+
+---
+name: test_ldwrdptrpi
+body: |
+ bb.0.entry:
+
+ ; CHECK-LABEL: test_ldwrdptrpi
+
+ ; CHECK: early-clobber %r0, early-clobber %r31r30 = LDRdPtrPi killed %r31r30
+ ; CHECK-NEXT: early-clobber %r1, early-clobber %r31r30 = LDRdPtrPi killed %r31r30
+
+ %r1r0, %r31r30 = LDWRdPtrPi %r31r30
+...
Added: llvm/trunk/test/CodeGen/AVR/pseudo/LPMWRdZ.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/LPMWRdZ.mir?rev=289191&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/LPMWRdZ.mir (added)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/LPMWRdZ.mir Fri Dec 9 01:49:04 2016
@@ -0,0 +1,22 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# XFAIL: *
+
+# This instruction is currently unimplemented.
+
+--- |
+ target triple = "avr--"
+ define void @test() {
+ entry:
+ ret void
+ }
+...
+
+---
+name: test
+body: |
+ bb.0.entry:
+
+ ; CHECK-LABEL: test
+
+ %r5r4 = LPMWRdZ %r31r30
+...
Added: llvm/trunk/test/CodeGen/AVR/pseudo/LPMWRdZPi.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/LPMWRdZPi.mir?rev=289191&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/LPMWRdZPi.mir (added)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/LPMWRdZPi.mir Fri Dec 9 01:49:04 2016
@@ -0,0 +1,22 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# XFAIL: *
+
+# This instruction is currently unimplemented.
+
+--- |
+ target triple = "avr--"
+ define void @test() {
+ entry:
+ ret void
+ }
+...
+
+---
+name: test
+body: |
+ bb.0.entry:
+
+ ; CHECK-LABEL: test
+
+ %r5r4 = LPMWRdZPi %r31r30, implicit-def %r31r30
+...
Added: llvm/trunk/test/CodeGen/AVR/pseudo/LSLWRd.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/LSLWRd.mir?rev=289191&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/LSLWRd.mir (added)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/LSLWRd.mir Fri Dec 9 01:49:04 2016
@@ -0,0 +1,22 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+
+--- |
+ target triple = "avr--"
+ define void @test() {
+ entry:
+ ret void
+ }
+...
+
+---
+name: test
+body: |
+ bb.0.entry:
+
+ ; CHECK-LABEL: test
+
+ ; CHECK: %r14 = LSLRd %r14, implicit-def %sreg
+ ; CHECK-NEXT: %r15 = ROLRd %r15, implicit-def %sreg, implicit killed %sreg
+
+ %r15r14 = LSLWRd %r15r14, implicit-def %sreg
+...
Added: llvm/trunk/test/CodeGen/AVR/pseudo/LSRWRd.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/LSRWRd.mir?rev=289191&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/LSRWRd.mir (added)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/LSRWRd.mir Fri Dec 9 01:49:04 2016
@@ -0,0 +1,22 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+
+--- |
+ target triple = "avr--"
+ define void @test() {
+ entry:
+ ret void
+ }
+...
+
+---
+name: test
+body: |
+ bb.0.entry:
+
+ ; CHECK-LABEL: test
+
+ ; CHECK: %r15 = LSRRd %r15, implicit-def %sreg
+ ; CHECK-NEXT: %r14 = RORRd %r14, implicit-def %sreg, implicit killed %sreg
+
+ %r15r14 = LSRWRd %r15r14, implicit-def %sreg
+...
Added: llvm/trunk/test/CodeGen/AVR/pseudo/OUTWARr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/OUTWARr.mir?rev=289191&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/OUTWARr.mir (added)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/OUTWARr.mir Fri Dec 9 01:49:04 2016
@@ -0,0 +1,22 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+
+--- |
+ target triple = "avr--"
+ define void @test() {
+ entry:
+ ret void
+ }
+...
+
+---
+name: test
+body: |
+ bb.0.entry:
+
+ ; CHECK-LABEL: test
+
+ ; CHECK: OUTARr 32, %r15
+ ; CHECK-NEXT: OUTARr 31, %r14
+
+ OUTWARr 31, %r15r14
+...
Added: llvm/trunk/test/CodeGen/AVR/pseudo/POPWRd.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/POPWRd.mir?rev=289191&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/POPWRd.mir (added)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/POPWRd.mir Fri Dec 9 01:49:04 2016
@@ -0,0 +1,22 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+
+--- |
+ target triple = "avr--"
+ define void @test() {
+ entry:
+ ret void
+ }
+...
+
+---
+name: test
+body: |
+ bb.0.entry:
+
+ ; CHECK-LABEL: test
+
+ ; CHECK: %r29 = POPRd implicit-def %sp, implicit %sp
+ ; CHECK-LABEL: %r28 = POPRd implicit-def %sp, implicit %sp
+
+ %r29r28 = POPWRd implicit-def %sp, implicit %sp
+...
Added: llvm/trunk/test/CodeGen/AVR/pseudo/PUSHWRr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/PUSHWRr.mir?rev=289191&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/PUSHWRr.mir (added)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/PUSHWRr.mir Fri Dec 9 01:49:04 2016
@@ -0,0 +1,22 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+
+--- |
+ target triple = "avr--"
+ define void @test() {
+ entry:
+ ret void
+ }
+...
+
+---
+name: test
+body: |
+ bb.0.entry:
+
+ ; CHECK-LABEL: test
+
+ ; CHECK: PUSHRr %r28, implicit-def %sp, implicit %sp
+ ; CHECK-NEXT: PUSHRr %r29, implicit-def %sp, implicit %sp
+
+ PUSHWRr %r29r28, implicit-def %sp, implicit %sp
+...
Added: llvm/trunk/test/CodeGen/AVR/pseudo/ROLWRd.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/ROLWRd.mir?rev=289191&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/ROLWRd.mir (added)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/ROLWRd.mir Fri Dec 9 01:49:04 2016
@@ -0,0 +1,22 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# XFAIL: *
+
+# This instruction is unimplemented.
+
+--- |
+ target triple = "avr--"
+ define void @test() {
+ entry:
+ ret void
+ }
+...
+
+---
+name: test
+body: |
+ bb.0.entry:
+
+ ; CHECK-LABEL: test
+
+ %r15r14 = ROLWRd %r15r14, implicit-def %sreg, implicit %sreg
+...
Added: llvm/trunk/test/CodeGen/AVR/pseudo/RORWRd.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/RORWRd.mir?rev=289191&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/RORWRd.mir (added)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/RORWRd.mir Fri Dec 9 01:49:04 2016
@@ -0,0 +1,22 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# XFAIL: *
+
+# This instruction is unimplemented.
+
+--- |
+ target triple = "avr--"
+ define void @test() {
+ entry:
+ ret void
+ }
+...
+
+---
+name: test
+body: |
+ bb.0.entry:
+
+ ; CHECK-LABEL: test
+
+ %r15r14 = RORWRd %r15r14, implicit-def %sreg, implicit %sreg
+...
Added: llvm/trunk/test/CodeGen/AVR/pseudo/SEXT.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/SEXT.mir?rev=289191&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/SEXT.mir (added)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/SEXT.mir Fri Dec 9 01:49:04 2016
@@ -0,0 +1,24 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+
+--- |
+ target triple = "avr--"
+ define void @test() {
+ entry:
+ ret void
+ }
+...
+
+---
+name: test
+body: |
+ bb.0.entry:
+
+ ; CHECK-LABEL: test
+
+ ; CHECK: %r14 = MOVRdRr %r31
+ ; CHECK-NEXT: %r15 = MOVRdRr %r31
+ ; CHECK-NEXT: %r15 = LSLRd killed %r15, implicit-def %sreg
+ ; CHECK-NEXT: %r15 = SBCRdRr killed %r15, killed %r15, implicit-def %sreg, implicit killed %sreg
+
+ %r15r14 = SEXT %r31, implicit-def %sreg
+...
Added: llvm/trunk/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir?rev=289191&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir (added)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir Fri Dec 9 01:49:04 2016
@@ -0,0 +1,22 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+
+--- |
+ target triple = "avr--"
+ define void @test() {
+ entry:
+ ret void
+ }
+...
+
+---
+name: test
+body: |
+ bb.0.entry:
+
+ ; CHECK-LABEL: test
+
+ ; CHECK: STDPtrQRr %r29r28, 10, %r0
+ ; CHECK-NEXT: STDPtrQRr %r29r28, 11, %r1
+
+ STDWPtrQRr %r29r28, 10, %r1r0
+...
Added: llvm/trunk/test/CodeGen/AVR/pseudo/STSWKRr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/STSWKRr.mir?rev=289191&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/STSWKRr.mir (added)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/STSWKRr.mir Fri Dec 9 01:49:04 2016
@@ -0,0 +1,24 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+
+# This test checks the expansion of the 16-bit STSWRdK pseudo instruction.
+
+--- |
+ target triple = "avr--"
+ define void @test_stswkrr() {
+ entry:
+ ret void
+ }
+...
+
+---
+name: test_stswkrr
+body: |
+ bb.0.entry:
+
+ ; CHECK-LABEL: test_stswkrr
+
+ ; CHECK: STSKRr 2560, %r31
+ ; CHECK-NEXT: STSKRr 2559, %r30
+
+ STSWKRr 2559, %r31r30
+...
Added: llvm/trunk/test/CodeGen/AVR/pseudo/STWPtrPdRr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/STWPtrPdRr.mir?rev=289191&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/STWPtrPdRr.mir (added)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/STWPtrPdRr.mir Fri Dec 9 01:49:04 2016
@@ -0,0 +1,22 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+
+--- |
+ target triple = "avr--"
+ define void @test() {
+ entry:
+ ret void
+ }
+...
+
+---
+name: test
+body: |
+ bb.0.entry:
+
+ ; CHECK-LABEL: test
+
+ ; CHECK: early-clobber %r31r30 = STPtrPdRr killed %r31r30, %r29, 52
+ ; CHECK-NEXT: early-clobber %r31r30 = STPtrPdRr killed %r31r30, %r28, 52
+
+ %r31r30 = STWPtrPdRr %r31r30, %r29r28, 52
+...
Added: llvm/trunk/test/CodeGen/AVR/pseudo/STWPtrPiRr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/STWPtrPiRr.mir?rev=289191&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/STWPtrPiRr.mir (added)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/STWPtrPiRr.mir Fri Dec 9 01:49:04 2016
@@ -0,0 +1,22 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+
+--- |
+ target triple = "avr--"
+ define void @test() {
+ entry:
+ ret void
+ }
+...
+
+---
+name: test
+body: |
+ bb.0.entry:
+
+ ; CHECK-LABEL: test
+
+ ; CHECK: early-clobber %r31r30 = STPtrPiRr killed %r31r30, %r28, 52
+ ; CHECK-NEXT: early-clobber %r31r30 = STPtrPiRr killed %r31r30, %r29, 52
+
+ %r31r30 = STWPtrPiRr %r31r30, %r29r28, 52
+...
Added: llvm/trunk/test/CodeGen/AVR/pseudo/STWPtrRr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/STWPtrRr.mir?rev=289191&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/STWPtrRr.mir (added)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/STWPtrRr.mir Fri Dec 9 01:49:04 2016
@@ -0,0 +1,24 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+
+# This test checks the expansion of the 16-bit STSWRdK pseudo instruction.
+
+--- |
+ target triple = "avr--"
+ define void @test_stwptrrr() {
+ entry:
+ ret void
+ }
+...
+
+---
+name: test_stwptrrr
+body: |
+ bb.0.entry:
+
+ ; CHECK-LABEL: test_stwptrrr
+
+ ; CHECK: STPtrRr %r31r30, %r16
+ ; CHECK-NEXT: STDPtrQRr %r31r30, 1, %r17
+
+ STWPtrRr %r31r30, %r17r16
+...
Added: llvm/trunk/test/CodeGen/AVR/pseudo/ZEXT.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/ZEXT.mir?rev=289191&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/ZEXT.mir (added)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/ZEXT.mir Fri Dec 9 01:49:04 2016
@@ -0,0 +1,24 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+
+--- |
+ target triple = "avr--"
+ define void @test() {
+ entry:
+ ret void
+ }
+...
+
+---
+name: test
+body: |
+ bb.0.entry:
+
+ ; CHECK-LABEL: test
+
+ ; CHECK: %r14 = MOVRdRr %r31
+ ; CHECK-NEXT: %r15 = MOVRdRr %r31
+ ; CHECK-NEXT: %r15 = LSLRd killed %r15, implicit-def %sreg
+ ; CHECK-NEXT: %r15 = SBCRdRr killed %r15, killed %r15, implicit-def %sreg, implicit killed %sreg
+
+ %r15r14 = SEXT %r31, implicit-def %sreg
+...
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