[llvm] r288985 - GlobalISel: use correct builder for ConstantExprs.
Tim Northover via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 7 13:29:16 PST 2016
Author: tnorthover
Date: Wed Dec 7 15:29:15 2016
New Revision: 288985
URL: http://llvm.org/viewvc/llvm-project?rev=288985&view=rev
Log:
GlobalISel: use correct builder for ConstantExprs.
ConstantExpr instances were emitting code into the current block rather than
the entry block. This meant they didn't necessarily dominate all uses, which is
clearly wrong.
Modified:
llvm/trunk/include/llvm/CodeGen/GlobalISel/IRTranslator.h
llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp
llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
Modified: llvm/trunk/include/llvm/CodeGen/GlobalISel/IRTranslator.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/GlobalISel/IRTranslator.h?rev=288985&r1=288984&r2=288985&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/GlobalISel/IRTranslator.h (original)
+++ llvm/trunk/include/llvm/CodeGen/GlobalISel/IRTranslator.h Wed Dec 7 15:29:15 2016
@@ -83,7 +83,7 @@ private:
/// @{
/// Translate \p Inst into its corresponding MachineInstr instruction(s).
- /// Insert the newly translated instruction(s) right where the MIRBuilder
+ /// Insert the newly translated instruction(s) right where the CurBuilder
/// is set.
///
/// The general algorithm is:
@@ -114,50 +114,53 @@ private:
/// Translate an LLVM bitcast into generic IR. Either a COPY or a G_BITCAST is
/// emitted.
- bool translateBitCast(const User &U);
+ bool translateBitCast(const User &U, MachineIRBuilder &MIRBuilder);
/// Translate an LLVM load instruction into generic IR.
- bool translateLoad(const User &U);
+ bool translateLoad(const User &U, MachineIRBuilder &MIRBuilder);
/// Translate an LLVM store instruction into generic IR.
- bool translateStore(const User &U);
+ bool translateStore(const User &U, MachineIRBuilder &MIRBuilder);
- bool translateMemcpy(const CallInst &CI);
+ bool translateMemcpy(const CallInst &CI, MachineIRBuilder &MIRBuilder);
- void getStackGuard(unsigned DstReg);
+ void getStackGuard(unsigned DstReg, MachineIRBuilder &MIRBuilder);
- bool translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID);
+ bool translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
+ MachineIRBuilder &MIRBuilder);
/// Translate call instruction.
/// \pre \p U is a call instruction.
- bool translateCall(const User &U);
+ bool translateCall(const User &U, MachineIRBuilder &MIRBuilder);
- bool translateInvoke(const User &U);
+ bool translateInvoke(const User &U, MachineIRBuilder &MIRBuilder);
- bool translateLandingPad(const User &U);
+ bool translateLandingPad(const User &U, MachineIRBuilder &MIRBuilder);
/// Translate one of LLVM's cast instructions into MachineInstrs, with the
/// given generic Opcode.
- bool translateCast(unsigned Opcode, const User &U);
+ bool translateCast(unsigned Opcode, const User &U,
+ MachineIRBuilder &MIRBuilder);
/// Translate static alloca instruction (i.e. one of constant size and in the
/// first basic block).
- bool translateStaticAlloca(const AllocaInst &Inst);
+ bool translateStaticAlloca(const AllocaInst &Inst,
+ MachineIRBuilder &MIRBuilder);
/// Translate a phi instruction.
- bool translatePHI(const User &U);
+ bool translatePHI(const User &U, MachineIRBuilder &MIRBuilder);
/// Translate a comparison (icmp or fcmp) instruction or constant.
- bool translateCompare(const User &U);
+ bool translateCompare(const User &U, MachineIRBuilder &MIRBuilder);
/// Translate an integer compare instruction (or constant).
- bool translateICmp(const User &U) {
- return translateCompare(U);
+ bool translateICmp(const User &U, MachineIRBuilder &MIRBuilder) {
+ return translateCompare(U, MIRBuilder);
}
/// Translate a floating-point compare instruction (or constant).
- bool translateFCmp(const User &U) {
- return translateCompare(U);
+ bool translateFCmp(const User &U, MachineIRBuilder &MIRBuilder) {
+ return translateCompare(U, MIRBuilder);
}
@@ -167,146 +170,182 @@ private:
/// Translate \p Inst into a binary operation \p Opcode.
/// \pre \p U is a binary operation.
- bool translateBinaryOp(unsigned Opcode, const User &U);
+ bool translateBinaryOp(unsigned Opcode, const User &U,
+ MachineIRBuilder &MIRBuilder);
/// Translate branch (br) instruction.
/// \pre \p U is a branch instruction.
- bool translateBr(const User &U);
+ bool translateBr(const User &U, MachineIRBuilder &MIRBuilder);
- bool translateExtractValue(const User &U);
+ bool translateExtractValue(const User &U, MachineIRBuilder &MIRBuilder);
- bool translateInsertValue(const User &U);
+ bool translateInsertValue(const User &U, MachineIRBuilder &MIRBuilder);
- bool translateSelect(const User &U);
+ bool translateSelect(const User &U, MachineIRBuilder &MIRBuilder);
- bool translateGetElementPtr(const User &U);
+ bool translateGetElementPtr(const User &U, MachineIRBuilder &MIRBuilder);
/// Translate return (ret) instruction.
/// The target needs to implement CallLowering::lowerReturn for
/// this to succeed.
/// \pre \p U is a return instruction.
- bool translateRet(const User &U);
+ bool translateRet(const User &U, MachineIRBuilder &MIRBuilder);
- bool translateAdd(const User &U) {
- return translateBinaryOp(TargetOpcode::G_ADD, U);
+ bool translateAdd(const User &U, MachineIRBuilder &MIRBuilder) {
+ return translateBinaryOp(TargetOpcode::G_ADD, U, MIRBuilder);
}
- bool translateSub(const User &U) {
- return translateBinaryOp(TargetOpcode::G_SUB, U);
+ bool translateSub(const User &U, MachineIRBuilder &MIRBuilder) {
+ return translateBinaryOp(TargetOpcode::G_SUB, U, MIRBuilder);
}
- bool translateAnd(const User &U) {
- return translateBinaryOp(TargetOpcode::G_AND, U);
+ bool translateAnd(const User &U, MachineIRBuilder &MIRBuilder) {
+ return translateBinaryOp(TargetOpcode::G_AND, U, MIRBuilder);
}
- bool translateMul(const User &U) {
- return translateBinaryOp(TargetOpcode::G_MUL, U);
+ bool translateMul(const User &U, MachineIRBuilder &MIRBuilder) {
+ return translateBinaryOp(TargetOpcode::G_MUL, U, MIRBuilder);
}
- bool translateOr(const User &U) {
- return translateBinaryOp(TargetOpcode::G_OR, U);
+ bool translateOr(const User &U, MachineIRBuilder &MIRBuilder) {
+ return translateBinaryOp(TargetOpcode::G_OR, U, MIRBuilder);
}
- bool translateXor(const User &U) {
- return translateBinaryOp(TargetOpcode::G_XOR, U);
+ bool translateXor(const User &U, MachineIRBuilder &MIRBuilder) {
+ return translateBinaryOp(TargetOpcode::G_XOR, U, MIRBuilder);
}
- bool translateUDiv(const User &U) {
- return translateBinaryOp(TargetOpcode::G_UDIV, U);
+ bool translateUDiv(const User &U, MachineIRBuilder &MIRBuilder) {
+ return translateBinaryOp(TargetOpcode::G_UDIV, U, MIRBuilder);
}
- bool translateSDiv(const User &U) {
- return translateBinaryOp(TargetOpcode::G_SDIV, U);
+ bool translateSDiv(const User &U, MachineIRBuilder &MIRBuilder) {
+ return translateBinaryOp(TargetOpcode::G_SDIV, U, MIRBuilder);
}
- bool translateURem(const User &U) {
- return translateBinaryOp(TargetOpcode::G_UREM, U);
+ bool translateURem(const User &U, MachineIRBuilder &MIRBuilder) {
+ return translateBinaryOp(TargetOpcode::G_UREM, U, MIRBuilder);
}
- bool translateSRem(const User &U) {
- return translateBinaryOp(TargetOpcode::G_SREM, U);
+ bool translateSRem(const User &U, MachineIRBuilder &MIRBuilder) {
+ return translateBinaryOp(TargetOpcode::G_SREM, U, MIRBuilder);
}
-
- bool translateAlloca(const User &U) {
- return translateStaticAlloca(cast<AllocaInst>(U));
+ bool translateAlloca(const User &U, MachineIRBuilder &MIRBuilder) {
+ return translateStaticAlloca(cast<AllocaInst>(U), MIRBuilder);
}
- bool translateIntToPtr(const User &U) {
- return translateCast(TargetOpcode::G_INTTOPTR, U);
+ bool translateIntToPtr(const User &U, MachineIRBuilder &MIRBuilder) {
+ return translateCast(TargetOpcode::G_INTTOPTR, U, MIRBuilder);
}
- bool translatePtrToInt(const User &U) {
- return translateCast(TargetOpcode::G_PTRTOINT, U);
+ bool translatePtrToInt(const User &U, MachineIRBuilder &MIRBuilder) {
+ return translateCast(TargetOpcode::G_PTRTOINT, U, MIRBuilder);
}
- bool translateTrunc(const User &U) {
- return translateCast(TargetOpcode::G_TRUNC, U);
+ bool translateTrunc(const User &U, MachineIRBuilder &MIRBuilder) {
+ return translateCast(TargetOpcode::G_TRUNC, U, MIRBuilder);
}
- bool translateFPTrunc(const User &U) {
- return translateCast(TargetOpcode::G_FPTRUNC, U);
+ bool translateFPTrunc(const User &U, MachineIRBuilder &MIRBuilder) {
+ return translateCast(TargetOpcode::G_FPTRUNC, U, MIRBuilder);
}
- bool translateFPExt(const User &U) {
- return translateCast(TargetOpcode::G_FPEXT, U);
+ bool translateFPExt(const User &U, MachineIRBuilder &MIRBuilder) {
+ return translateCast(TargetOpcode::G_FPEXT, U, MIRBuilder);
}
- bool translateFPToUI(const User &U) {
- return translateCast(TargetOpcode::G_FPTOUI, U);
+ bool translateFPToUI(const User &U, MachineIRBuilder &MIRBuilder) {
+ return translateCast(TargetOpcode::G_FPTOUI, U, MIRBuilder);
}
- bool translateFPToSI(const User &U) {
- return translateCast(TargetOpcode::G_FPTOSI, U);
+ bool translateFPToSI(const User &U, MachineIRBuilder &MIRBuilder) {
+ return translateCast(TargetOpcode::G_FPTOSI, U, MIRBuilder);
}
- bool translateUIToFP(const User &U) {
- return translateCast(TargetOpcode::G_UITOFP, U);
+ bool translateUIToFP(const User &U, MachineIRBuilder &MIRBuilder) {
+ return translateCast(TargetOpcode::G_UITOFP, U, MIRBuilder);
}
- bool translateSIToFP(const User &U) {
- return translateCast(TargetOpcode::G_SITOFP, U);
+ bool translateSIToFP(const User &U, MachineIRBuilder &MIRBuilder) {
+ return translateCast(TargetOpcode::G_SITOFP, U, MIRBuilder);
}
-
- bool translateUnreachable(const User &U) { return true; }
-
- bool translateSExt(const User &U) {
- return translateCast(TargetOpcode::G_SEXT, U);
+ bool translateUnreachable(const User &U, MachineIRBuilder &MIRBuilder) {
+ return true;
+ }
+ bool translateSExt(const User &U, MachineIRBuilder &MIRBuilder) {
+ return translateCast(TargetOpcode::G_SEXT, U, MIRBuilder);
}
- bool translateZExt(const User &U) {
- return translateCast(TargetOpcode::G_ZEXT, U);
+ bool translateZExt(const User &U, MachineIRBuilder &MIRBuilder) {
+ return translateCast(TargetOpcode::G_ZEXT, U, MIRBuilder);
}
- bool translateShl(const User &U) {
- return translateBinaryOp(TargetOpcode::G_SHL, U);
+ bool translateShl(const User &U, MachineIRBuilder &MIRBuilder) {
+ return translateBinaryOp(TargetOpcode::G_SHL, U, MIRBuilder);
}
- bool translateLShr(const User &U) {
- return translateBinaryOp(TargetOpcode::G_LSHR, U);
+ bool translateLShr(const User &U, MachineIRBuilder &MIRBuilder) {
+ return translateBinaryOp(TargetOpcode::G_LSHR, U, MIRBuilder);
}
- bool translateAShr(const User &U) {
- return translateBinaryOp(TargetOpcode::G_ASHR, U);
+ bool translateAShr(const User &U, MachineIRBuilder &MIRBuilder) {
+ return translateBinaryOp(TargetOpcode::G_ASHR, U, MIRBuilder);
}
- bool translateFAdd(const User &U) {
- return translateBinaryOp(TargetOpcode::G_FADD, U);
+ bool translateFAdd(const User &U, MachineIRBuilder &MIRBuilder) {
+ return translateBinaryOp(TargetOpcode::G_FADD, U, MIRBuilder);
}
- bool translateFSub(const User &U) {
- return translateBinaryOp(TargetOpcode::G_FSUB, U);
+ bool translateFSub(const User &U, MachineIRBuilder &MIRBuilder) {
+ return translateBinaryOp(TargetOpcode::G_FSUB, U, MIRBuilder);
}
- bool translateFMul(const User &U) {
- return translateBinaryOp(TargetOpcode::G_FMUL, U);
+ bool translateFMul(const User &U, MachineIRBuilder &MIRBuilder) {
+ return translateBinaryOp(TargetOpcode::G_FMUL, U, MIRBuilder);
}
- bool translateFDiv(const User &U) {
- return translateBinaryOp(TargetOpcode::G_FDIV, U);
+ bool translateFDiv(const User &U, MachineIRBuilder &MIRBuilder) {
+ return translateBinaryOp(TargetOpcode::G_FDIV, U, MIRBuilder);
}
- bool translateFRem(const User &U) {
- return translateBinaryOp(TargetOpcode::G_FREM, U);
+ bool translateFRem(const User &U, MachineIRBuilder &MIRBuilder) {
+ return translateBinaryOp(TargetOpcode::G_FREM, U, MIRBuilder);
}
// Stubs to keep the compiler happy while we implement the rest of the
// translation.
- bool translateSwitch(const User &U) { return false; }
- bool translateIndirectBr(const User &U) { return false; }
- bool translateResume(const User &U) { return false; }
- bool translateCleanupRet(const User &U) { return false; }
- bool translateCatchRet(const User &U) { return false; }
- bool translateCatchSwitch(const User &U) { return false; }
- bool translateFence(const User &U) { return false; }
- bool translateAtomicCmpXchg(const User &U) { return false; }
- bool translateAtomicRMW(const User &U) { return false; }
- bool translateAddrSpaceCast(const User &U) { return false; }
- bool translateCleanupPad(const User &U) { return false; }
- bool translateCatchPad(const User &U) { return false; }
- bool translateUserOp1(const User &U) { return false; }
- bool translateUserOp2(const User &U) { return false; }
- bool translateVAArg(const User &U) { return false; }
- bool translateExtractElement(const User &U) { return false; }
- bool translateInsertElement(const User &U) { return false; }
- bool translateShuffleVector(const User &U) { return false; }
+ bool translateSwitch(const User &U, MachineIRBuilder &MIRBuilder) {
+ return false;
+ }
+ bool translateIndirectBr(const User &U, MachineIRBuilder &MIRBuilder) {
+ return false;
+ }
+ bool translateResume(const User &U, MachineIRBuilder &MIRBuilder) {
+ return false;
+ }
+ bool translateCleanupRet(const User &U, MachineIRBuilder &MIRBuilder) {
+ return false;
+ }
+ bool translateCatchRet(const User &U, MachineIRBuilder &MIRBuilder) {
+ return false;
+ }
+ bool translateCatchSwitch(const User &U, MachineIRBuilder &MIRBuilder) {
+ return false;
+ }
+ bool translateFence(const User &U, MachineIRBuilder &MIRBuilder) {
+ return false;
+ }
+ bool translateAtomicCmpXchg(const User &U, MachineIRBuilder &MIRBuilder) {
+ return false;
+ }
+ bool translateAtomicRMW(const User &U, MachineIRBuilder &MIRBuilder) {
+ return false;
+ }
+ bool translateAddrSpaceCast(const User &U, MachineIRBuilder &MIRBuilder) {
+ return false;
+ }
+ bool translateCleanupPad(const User &U, MachineIRBuilder &MIRBuilder) {
+ return false;
+ }
+ bool translateCatchPad(const User &U, MachineIRBuilder &MIRBuilder) {
+ return false;
+ }
+ bool translateUserOp1(const User &U, MachineIRBuilder &MIRBuilder) {
+ return false;
+ }
+ bool translateUserOp2(const User &U, MachineIRBuilder &MIRBuilder) {
+ return false;
+ }
+ bool translateVAArg(const User &U, MachineIRBuilder &MIRBuilder) {
+ return false;
+ }
+ bool translateExtractElement(const User &U, MachineIRBuilder &MIRBuilder) {
+ return false;
+ }
+ bool translateInsertElement(const User &U, MachineIRBuilder &MIRBuilder) {
+ return false;
+ }
+ bool translateShuffleVector(const User &U, MachineIRBuilder &MIRBuilder) {
+ return false;
+ }
/// @}
@@ -314,7 +353,7 @@ private:
// I.e., compared to regular MIBuilder, this one also inserts the instruction
// in the current block, it can creates block, etc., basically a kind of
// IRBuilder, but for Machine IR.
- MachineIRBuilder MIRBuilder;
+ MachineIRBuilder CurBuilder;
// Builder set to the entry block (just after ABI lowering instructions). Used
// as a convenient location for Constants.
Modified: llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp?rev=288985&r1=288984&r2=288985&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp Wed Dec 7 15:29:15 2016
@@ -131,7 +131,8 @@ MachineBasicBlock &IRTranslator::getOrCr
return *MBB;
}
-bool IRTranslator::translateBinaryOp(unsigned Opcode, const User &U) {
+bool IRTranslator::translateBinaryOp(unsigned Opcode, const User &U,
+ MachineIRBuilder &MIRBuilder) {
// FIXME: handle signed/unsigned wrapping flags.
// Get or create a virtual register for each value.
@@ -145,7 +146,8 @@ bool IRTranslator::translateBinaryOp(uns
return true;
}
-bool IRTranslator::translateCompare(const User &U) {
+bool IRTranslator::translateCompare(const User &U,
+ MachineIRBuilder &MIRBuilder) {
const CmpInst *CI = dyn_cast<CmpInst>(&U);
unsigned Op0 = getOrCreateVReg(*U.getOperand(0));
unsigned Op1 = getOrCreateVReg(*U.getOperand(1));
@@ -162,7 +164,7 @@ bool IRTranslator::translateCompare(cons
return true;
}
-bool IRTranslator::translateRet(const User &U) {
+bool IRTranslator::translateRet(const User &U, MachineIRBuilder &MIRBuilder) {
const ReturnInst &RI = cast<ReturnInst>(U);
const Value *Ret = RI.getReturnValue();
// The target may mess up with the insertion point, but
@@ -171,7 +173,7 @@ bool IRTranslator::translateRet(const Us
return CLI->lowerReturn(MIRBuilder, Ret, !Ret ? 0 : getOrCreateVReg(*Ret));
}
-bool IRTranslator::translateBr(const User &U) {
+bool IRTranslator::translateBr(const User &U, MachineIRBuilder &MIRBuilder) {
const BranchInst &BrInst = cast<BranchInst>(U);
unsigned Succ = 0;
if (!BrInst.isUnconditional()) {
@@ -193,7 +195,7 @@ bool IRTranslator::translateBr(const Use
return true;
}
-bool IRTranslator::translateLoad(const User &U) {
+bool IRTranslator::translateLoad(const User &U, MachineIRBuilder &MIRBuilder) {
const LoadInst &LI = cast<LoadInst>(U);
if (!TPC->isGlobalISelAbortEnabled() && LI.isAtomic())
@@ -215,7 +217,7 @@ bool IRTranslator::translateLoad(const U
return true;
}
-bool IRTranslator::translateStore(const User &U) {
+bool IRTranslator::translateStore(const User &U, MachineIRBuilder &MIRBuilder) {
const StoreInst &SI = cast<StoreInst>(U);
if (!TPC->isGlobalISelAbortEnabled() && SI.isAtomic())
@@ -240,7 +242,8 @@ bool IRTranslator::translateStore(const
return true;
}
-bool IRTranslator::translateExtractValue(const User &U) {
+bool IRTranslator::translateExtractValue(const User &U,
+ MachineIRBuilder &MIRBuilder) {
const Value *Src = U.getOperand(0);
Type *Int32Ty = Type::getInt32Ty(U.getContext());
SmallVector<Value *, 1> Indices;
@@ -265,7 +268,8 @@ bool IRTranslator::translateExtractValue
return true;
}
-bool IRTranslator::translateInsertValue(const User &U) {
+bool IRTranslator::translateInsertValue(const User &U,
+ MachineIRBuilder &MIRBuilder) {
const Value *Src = U.getOperand(0);
Type *Int32Ty = Type::getInt32Ty(U.getContext());
SmallVector<Value *, 1> Indices;
@@ -292,14 +296,16 @@ bool IRTranslator::translateInsertValue(
return true;
}
-bool IRTranslator::translateSelect(const User &U) {
+bool IRTranslator::translateSelect(const User &U,
+ MachineIRBuilder &MIRBuilder) {
MIRBuilder.buildSelect(getOrCreateVReg(U), getOrCreateVReg(*U.getOperand(0)),
getOrCreateVReg(*U.getOperand(1)),
getOrCreateVReg(*U.getOperand(2)));
return true;
}
-bool IRTranslator::translateBitCast(const User &U) {
+bool IRTranslator::translateBitCast(const User &U,
+ MachineIRBuilder &MIRBuilder) {
if (LLT{*U.getOperand(0)->getType(), *DL} == LLT{*U.getType(), *DL}) {
unsigned &Reg = ValToVReg[&U];
if (Reg)
@@ -308,17 +314,19 @@ bool IRTranslator::translateBitCast(cons
Reg = getOrCreateVReg(*U.getOperand(0));
return true;
}
- return translateCast(TargetOpcode::G_BITCAST, U);
+ return translateCast(TargetOpcode::G_BITCAST, U, MIRBuilder);
}
-bool IRTranslator::translateCast(unsigned Opcode, const User &U) {
+bool IRTranslator::translateCast(unsigned Opcode, const User &U,
+ MachineIRBuilder &MIRBuilder) {
unsigned Op = getOrCreateVReg(*U.getOperand(0));
unsigned Res = getOrCreateVReg(U);
MIRBuilder.buildInstr(Opcode).addDef(Res).addUse(Op);
return true;
}
-bool IRTranslator::translateGetElementPtr(const User &U) {
+bool IRTranslator::translateGetElementPtr(const User &U,
+ MachineIRBuilder &MIRBuilder) {
// FIXME: support vector GEPs.
if (U.getType()->isVectorTy())
return false;
@@ -388,7 +396,8 @@ bool IRTranslator::translateGetElementPt
return true;
}
-bool IRTranslator::translateMemcpy(const CallInst &CI) {
+bool IRTranslator::translateMemcpy(const CallInst &CI,
+ MachineIRBuilder &MIRBuilder) {
LLT SizeTy{*CI.getArgOperand(2)->getType(), *DL};
if (cast<PointerType>(CI.getArgOperand(0)->getType())->getAddressSpace() !=
0 ||
@@ -409,7 +418,8 @@ bool IRTranslator::translateMemcpy(const
CallLowering::ArgInfo(0, CI.getType()), Args);
}
-void IRTranslator::getStackGuard(unsigned DstReg) {
+void IRTranslator::getStackGuard(unsigned DstReg,
+ MachineIRBuilder &MIRBuilder) {
auto MIB = MIRBuilder.buildInstr(TargetOpcode::LOAD_STACK_GUARD);
MIB.addDef(DstReg);
@@ -428,8 +438,8 @@ void IRTranslator::getStackGuard(unsigne
MIB.setMemRefs(MemRefs, MemRefs + 1);
}
-bool IRTranslator::translateKnownIntrinsic(const CallInst &CI,
- Intrinsic::ID ID) {
+bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
+ MachineIRBuilder &MIRBuilder) {
unsigned Op = 0;
switch (ID) {
default: return false;
@@ -440,7 +450,7 @@ bool IRTranslator::translateKnownIntrins
case Intrinsic::umul_with_overflow: Op = TargetOpcode::G_UMULO; break;
case Intrinsic::smul_with_overflow: Op = TargetOpcode::G_SMULO; break;
case Intrinsic::memcpy:
- return translateMemcpy(CI);
+ return translateMemcpy(CI, MIRBuilder);
case Intrinsic::eh_typeid_for: {
GlobalValue *GV = ExtractTypeInfo(CI.getArgOperand(0));
unsigned Reg = getOrCreateVReg(CI);
@@ -456,12 +466,12 @@ bool IRTranslator::translateKnownIntrins
return true;
}
case Intrinsic::stackguard:
- getStackGuard(getOrCreateVReg(CI));
+ getStackGuard(getOrCreateVReg(CI), MIRBuilder);
return true;
case Intrinsic::stackprotector: {
LLT PtrTy{*CI.getArgOperand(0)->getType(), *DL};
unsigned GuardVal = MRI->createGenericVirtualRegister(PtrTy);
- getStackGuard(GuardVal);
+ getStackGuard(GuardVal, MIRBuilder);
AllocaInst *Slot = cast<AllocaInst>(CI.getArgOperand(1));
MIRBuilder.buildStore(
@@ -496,7 +506,7 @@ bool IRTranslator::translateKnownIntrins
return true;
}
-bool IRTranslator::translateCall(const User &U) {
+bool IRTranslator::translateCall(const User &U, MachineIRBuilder &MIRBuilder) {
const CallInst &CI = cast<CallInst>(U);
auto TII = MF->getTarget().getIntrinsicInfo();
const Function *F = CI.getCalledFunction();
@@ -518,7 +528,7 @@ bool IRTranslator::translateCall(const U
assert(ID != Intrinsic::not_intrinsic && "unknown intrinsic");
- if (translateKnownIntrinsic(CI, ID))
+ if (translateKnownIntrinsic(CI, ID, MIRBuilder))
return true;
unsigned Res = CI.getType()->isVoidTy() ? 0 : getOrCreateVReg(CI);
@@ -534,7 +544,8 @@ bool IRTranslator::translateCall(const U
return true;
}
-bool IRTranslator::translateInvoke(const User &U) {
+bool IRTranslator::translateInvoke(const User &U,
+ MachineIRBuilder &MIRBuilder) {
const InvokeInst &I = cast<InvokeInst>(U);
MCContext &Context = MF->getContext();
@@ -586,7 +597,8 @@ bool IRTranslator::translateInvoke(const
return true;
}
-bool IRTranslator::translateLandingPad(const User &U) {
+bool IRTranslator::translateLandingPad(const User &U,
+ MachineIRBuilder &MIRBuilder) {
const LandingPadInst &LP = cast<LandingPadInst>(U);
MachineBasicBlock &MBB = MIRBuilder.getMBB();
@@ -636,7 +648,8 @@ bool IRTranslator::translateLandingPad(c
return true;
}
-bool IRTranslator::translateStaticAlloca(const AllocaInst &AI) {
+bool IRTranslator::translateStaticAlloca(const AllocaInst &AI,
+ MachineIRBuilder &MIRBuilder) {
if (!TPC->isGlobalISelAbortEnabled() && !AI.isStaticAlloca())
return false;
@@ -647,7 +660,7 @@ bool IRTranslator::translateStaticAlloca
return true;
}
-bool IRTranslator::translatePHI(const User &U) {
+bool IRTranslator::translatePHI(const User &U, MachineIRBuilder &MIRBuilder) {
const PHINode &PI = cast<PHINode>(U);
auto MIB = MIRBuilder.buildInstr(TargetOpcode::PHI);
MIB.addDef(getOrCreateVReg(PI));
@@ -659,7 +672,7 @@ bool IRTranslator::translatePHI(const Us
void IRTranslator::finishPendingPhis() {
for (std::pair<const PHINode *, MachineInstr *> &Phi : PendingPHIs) {
const PHINode *PI = Phi.first;
- MachineInstrBuilder MIB(MIRBuilder.getMF(), Phi.second);
+ MachineInstrBuilder MIB(*MF, Phi.second);
// All MachineBasicBlocks exist, add them to the PHI. We assume IRTranslator
// won't create extra control flow here, otherwise we need to find the
@@ -675,10 +688,10 @@ void IRTranslator::finishPendingPhis() {
}
bool IRTranslator::translate(const Instruction &Inst) {
- MIRBuilder.setDebugLoc(Inst.getDebugLoc());
+ CurBuilder.setDebugLoc(Inst.getDebugLoc());
switch(Inst.getOpcode()) {
#define HANDLE_INST(NUM, OPCODE, CLASS) \
- case Instruction::OPCODE: return translate##OPCODE(Inst);
+ case Instruction::OPCODE: return translate##OPCODE(Inst, CurBuilder);
#include "llvm/IR/Instruction.def"
default:
if (!TPC->isGlobalISelAbortEnabled())
@@ -701,7 +714,7 @@ bool IRTranslator::translate(const Const
else if (auto CE = dyn_cast<ConstantExpr>(&C)) {
switch(CE->getOpcode()) {
#define HANDLE_INST(NUM, OPCODE, CLASS) \
- case Instruction::OPCODE: return translate##OPCODE(*CE);
+ case Instruction::OPCODE: return translate##OPCODE(*CE, EntryBuilder);
#include "llvm/IR/Instruction.def"
default:
if (!TPC->isGlobalISelAbortEnabled())
@@ -731,7 +744,7 @@ bool IRTranslator::runOnMachineFunction(
if (F.empty())
return false;
CLI = MF->getSubtarget().getCallLowering();
- MIRBuilder.setMF(*MF);
+ CurBuilder.setMF(*MF);
EntryBuilder.setMF(*MF);
MRI = &MF->getRegInfo();
DL = &F.getParent()->getDataLayout();
@@ -766,7 +779,7 @@ bool IRTranslator::runOnMachineFunction(
MachineBasicBlock &MBB = getOrCreateBB(BB);
// Set the insertion point of all the following translations to
// the end of this basic block.
- MIRBuilder.setMBB(MBB);
+ CurBuilder.setMBB(MBB);
for (const Instruction &Inst: BB) {
Succeeded &= translate(Inst);
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll?rev=288985&r1=288984&r2=288985&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll Wed Dec 7 15:29:15 2016
@@ -963,10 +963,9 @@ define i8* @test_const_placement() {
; CHECK-LABEL: name: test_const_placement
; CHECK: bb.0:
; CHECK: [[VAL_INT:%[0-9]+]](s32) = G_CONSTANT i32 42
+; CHECK: [[VAL:%[0-9]+]](p0) = G_INTTOPTR [[VAL_INT]](s32)
; CHECK: bb.1:
; CHECK: G_BR
-; CHECK: bb.2:
-; CHECK: [[VAL:%[0-9]+]](p0) = G_INTTOPTR [[VAL_INT]](s32)
br label %next
next:
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