[PATCH] D26743: Expandload and Compressing store - documentation update

[Ayal Zaks via Phabricator via llvm-commits]

Ayal added a comment.

This version of the documentation LGTM, thanks for addressing.

Michael, ok to land, given the discussion in http://lists.llvm.org/pipermail/llvm-dev/2016-September/104985.html?



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Comment at: ../docs/LangRef.rst:11857
+
+LLVM provides intrinsics for expanding load and compressing store operations. Data selected from a vector according to a mask is stored in consecutive memory addresses (compressed store), and vice-versa (expanding load). These operations effective map to "if (cond) a[j++] = v.i" and "if (cond) v.i = a[j++]" patterns, respectively. Note that when the mask starts with '1' bits followed by '0' bits, these operations are identical to :ref:`llvm.masked.store <int_mstore>` and :ref:`llvm.masked.load <int_mload>`.
+
----------------
May be clearer to write
 "if(cond) a[j++] = v.i" >>
 "if (cond.i) a[j++] = v.i"
and
"if (cond) v.i = a[j++]" >>
"if (cond.i) v.i = a[j++]"
showing the condition as a mask vector similar to the data vector.


Repository:
  rL LLVM

https://reviews.llvm.org/D26743