[llvm] r288861 - AMDGPU: Fix crash on i16 constant expression

[Matt Arsenault via llvm-commits]

Author: arsenm
Date: Tue Dec  6 17:18:06 2016
New Revision: 288861

URL: http://llvm.org/viewvc/llvm-project?rev=288861&view=rev
Log:
AMDGPU: Fix crash on i16 constant expression

Modified:
    llvm/trunk/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
    llvm/trunk/test/CodeGen/AMDGPU/amdgpu-codegenprepare-i16-to-i32.ll

Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp?rev=288861&r1=288860&r2=288861&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp Tue Dec  6 17:18:06 2016
@@ -146,9 +146,10 @@ public:
 
 Value *AMDGPUCodeGenPrepare::copyFlags(
     const BinaryOperator &I, Value *V) const {
-  assert(isa<BinaryOperator>(V) && "V must be binary operation");
+  BinaryOperator *BinOp = dyn_cast<BinaryOperator>(V);
+  if (!BinOp) // Possibly constant expression.
+    return V;
 
-  BinaryOperator *BinOp = cast<BinaryOperator>(V);
   if (isa<OverflowingBinaryOperator>(BinOp)) {
     BinOp->setHasNoSignedWrap(I.hasNoSignedWrap());
     BinOp->setHasNoUnsignedWrap(I.hasNoUnsignedWrap());

Modified: llvm/trunk/test/CodeGen/AMDGPU/amdgpu-codegenprepare-i16-to-i32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/amdgpu-codegenprepare-i16-to-i32.ll?rev=288861&r1=288860&r2=288861&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/amdgpu-codegenprepare-i16-to-i32.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/amdgpu-codegenprepare-i16-to-i32.ll Tue Dec  6 17:18:06 2016
@@ -533,6 +533,27 @@ define i16 @add_i16(i16 %a, i16 %b) {
   ret i16 %r
 }
 
+; GCN-LABEL: @constant_add_i16(
+; VI: ret i16 3
+define i16 @constant_add_i16() {
+  %r = add i16 1, 2
+  ret i16 %r
+}
+
+; GCN-LABEL: @constant_add_nsw_i16(
+; VI: ret i16 3
+define i16 @constant_add_nsw_i16() {
+  %r = add nsw i16 1, 2
+  ret i16 %r
+}
+
+; GCN-LABEL: @constant_add_nuw_i16(
+; VI: ret i16 3
+define i16 @constant_add_nuw_i16() {
+  %r = add nsw i16 1, 2
+  ret i16 %r
+}
+
 ; GCN-LABEL: @add_nsw_i16(
 ; SI: %r = add nsw i16 %a, %b
 ; SI-NEXT: ret i16 %r
@@ -806,6 +827,13 @@ define i16 @ashr_exact_i16(i16 %a, i16 %
   ret i16 %r
 }
 
+; GCN-LABEL: @constant_lshr_exact_i16(
+; VI: ret i16 2
+define i16 @constant_lshr_exact_i16(i16 %a, i16 %b) {
+  %r = lshr exact i16 4, 1
+  ret i16 %r
+}
+
 ; GCN-LABEL: @and_i16(
 ; SI: %r = and i16 %a, %b
 ; SI-NEXT: ret i16 %r