[PATCH] D27395: Fixed store operation for a vector of i1.

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

If you're going to put padding into `<4 x i1>` vectors, you're going to have to change the IR to match; getStoreSizeInBits() is currently 4 for `<4 x i1>`.

If we wanted bit-packed vectors, we could just ban masked.store for vectors whose elements aren't byte-aligned.


Repository:
  rL LLVM

https://reviews.llvm.org/D27395