[PATCH] D26506: Compiler-rt part of D26230: Add (constant) masked load/store support
Filipe Cabecinhas via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Dec 2 10:04:33 PST 2016
filcab added a comment.
I've tried pushing this test, but one of the buildbots (at least) doesn't have AVX support. And AVX/AVX2 are the only things on X86 that will generate those masked loads/stores.
I'd go with either:
No testing on compiler-rt (ASan doesn't behave differently in the face of masked ops, so we should be able to go by with only the tests from llvm)
Testing on compiler-rt using IR, *assuming* we can lower calls to masked.loads/stores even on non-AVX CPUs
Testing on compiler-rt using some other arch that's not X86 (I don't really have the hardware to try that out, though)
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