[PATCH] D27261: [SelectionDAG] Do not increment SDNodeOrder for debug intrinsics.

[Florian Hahn via Phabricator via llvm-commits]

fhahn created this revision.
fhahn added reviewers: danielcdh, echristo, bogner.
fhahn added a subscriber: llvm-commits.
Herald added subscribers: mehdi_amini, MatzeB.

  Some parts of CodeGen rely on the IR order (e.g. ScheduleDAGRRList)
  and debug intrinsics previously affected the ordering.
  
  This problem was found using check_cfc.py. With this patch, the build
  failures for llvm's test-suite with check_cfc.py go from 113 down to 77
  in x86_64.


https://reviews.llvm.org/D27261

Files:
  lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
  lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  test/CodeGen/X86/dbg_intrinsic_cfc.ll
  test/DebugInfo/X86/dbg-value-dag-combine.ll
  test/DebugInfo/X86/pieces-4.ll

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