[llvm] r288215 - [lanai] Manually match 0/-1 with R0/R1.

[Jacques Pienaar via llvm-commits]

Author: jpienaar
Date: Tue Nov 29 17:01:09 2016
New Revision: 288215

URL: http://llvm.org/viewvc/llvm-project?rev=288215&view=rev
Log:
[lanai] Manually match 0/-1 with R0/R1.

Summary: Previously 0 and -1 was matched via tablegen rules. But this could cause problems where a physical register was being used where a virtual register was expected (seen in optimizeSelect and TwoAddressInstructionPass). Instead follow AArch64 and match in DAGToDAGISel.

Reviewers: eliben, majnemer

Subscribers: llvm-commits, aemerson

Differential Revision: https://reviews.llvm.org/D27171

Modified:
    llvm/trunk/lib/Target/Lanai/LanaiISelDAGToDAG.cpp
    llvm/trunk/lib/Target/Lanai/LanaiInstrInfo.td
    llvm/trunk/test/CodeGen/Lanai/constant_multiply.ll

Modified: llvm/trunk/lib/Target/Lanai/LanaiISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Lanai/LanaiISelDAGToDAG.cpp?rev=288215&r1=288214&r2=288215&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Lanai/LanaiISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Lanai/LanaiISelDAGToDAG.cpp Tue Nov 29 17:01:09 2016
@@ -282,9 +282,29 @@ void LanaiDAGToDAGISel::Select(SDNode *N
     return;
   }
 
-  // Instruction Selection not handled by the auto-generated
-  // tablegen selection should be handled here.
+  // Instruction Selection not handled by the auto-generated tablegen selection
+  // should be handled here.
+  EVT VT = Node->getValueType(0);
   switch (Opcode) {
+  case ISD::Constant:
+    if (VT == MVT::i32) {
+      ConstantSDNode *ConstNode = cast<ConstantSDNode>(Node);
+      // Materialize zero constants as copies from R0. This allows the coalescer
+      // to propagate these into other instructions.
+      if (ConstNode->isNullValue()) {
+        SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
+                                             SDLoc(Node), Lanai::R0, MVT::i32);
+        return ReplaceNode(Node, New.getNode());
+      }
+      // Materialize all ones constants as copies from R1. This allows the
+      // coalescer to propagate these into other instructions.
+      if (ConstNode->isAllOnesValue()) {
+        SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
+                                             SDLoc(Node), Lanai::R1, MVT::i32);
+        return ReplaceNode(Node, New.getNode());
+      }
+    }
+    break;
   case ISD::FrameIndex:
     selectFrameIndex(Node);
     return;

Modified: llvm/trunk/lib/Target/Lanai/LanaiInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Lanai/LanaiInstrInfo.td?rev=288215&r1=288214&r2=288215&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Lanai/LanaiInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Lanai/LanaiInstrInfo.td Tue Nov 29 17:01:09 2016
@@ -831,11 +831,6 @@ def TRAILZ : InstSpecial<0b011, (outs GP
 // Non-Instruction Patterns
 //===----------------------------------------------------------------------===//
 
-// i32 0 and R0 can be used interchangeably.
-def : Pat<(i32 0), (i32 R0)>;
-// i32 -1 and R1 can be used interchangeably.
-def : Pat<(i32 -1), (i32 R1)>;
-
 // unsigned 16-bit immediate
 def : Pat<(i32 i32lo16z:$imm), (OR_I_LO (i32 R0), imm:$imm)>;
 

Modified: llvm/trunk/test/CodeGen/Lanai/constant_multiply.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Lanai/constant_multiply.ll?rev=288215&r1=288214&r2=288215&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Lanai/constant_multiply.ll (original)
+++ llvm/trunk/test/CodeGen/Lanai/constant_multiply.ll Tue Nov 29 17:01:09 2016
@@ -81,18 +81,18 @@ define i32 @fm8(i32 inreg %a) #0 {
 }
 
 ; CHECK-LABEL: fm9:
-; CHECK: sh %r6, 0x3, %r{{[0-9]+}}
-; CHECK: sub %r{{[0-9]+}}, %r6, %r{{[0-9]+}}
-; CHECK: sub %r{{[0-9]+}}, %r{{[0-9]+}}, %rv
+; CHECK: sub	%r0, %r6, %r{{[0-9]+}}
+; CHECK: sh	%r6, 0x3, %r9
+; CHECK: sub	%r{{[0-9]+}}, %r9, %rv
 define i32 @fm9(i32 inreg %a) #0 {
   %1 = mul nsw i32 %a, -9
   ret i32 %1
 }
 
 ; CHECK-LABEL: fm10:
-; CHECK: sh %r6, 0x3, %r{{[0-9]+}}
 ; CHECK: sh %r6, 0x1, %r{{[0-9]+}}
 ; CHECK: sub %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}
+; CHECK: sh %r6, 0x3, %r{{[0-9]+}}
 ; CHECK: sub %r{{[0-9]+}}, %r{{[0-9]+}}, %rv
 define i32 @fm10(i32 inreg %a) #0 {
   %1 = mul nsw i32 %a, -10